FEDEVEL
Platform forum

Mihai , 08-20-2019, 08:53 AM

Hi,

I am routing a 100 MB/s Ethernet PHY using both RMII and MII configuration and while searching for some layout guidelines I came across with these 2 documents which are somehow contradictory:

1- this one, click, from Cadence which says that the data lines and the clocks should be length matched.
2-and this one, click, from TI, which says that the lines should not have more that 2 inch difference in length between them. See section 5.2 at page 8, 3rd paragraph.


Should I really care enough to length mach these signals?

Cheers,
Mihai

robertferanec , 08-21-2019, 05:26 AM

If I remember right, this depends on silicon and specific chip. I believe, older specification needed PCB adjustment (different lengths of tracks), however new specification should use the same track lengths and compensation can be done inside of the chip (you can set delay in registers). So the best is to check datasheet of specific PHY what you are going to use.

Paul van Avesaath , 08-21-2019, 06:08 AM

also one of your links is from july 2019 anmd the other is a document from 2006... todays IC design is a lot more capable than it used to be...
always check your source of info. it might be out of date..
and like @robertferanec says it depends on the chip how you route it.. in these cases there is always a section in the datasheet with layout recommendations. or there are reference kits aviable were you can have a peak at how they do the layout.

Mihai , 08-23-2019, 12:45 AM

Dear @robertferanec and @Paul van Avesaath,

Many thanks. Indeed that's also my conclusions after studying other datasheets. I am using an older chip, DP83848x, which the vendor specifies in its datasheet that the MII and RMII should be length matched within 2 inch. However, I have matched them tight. I was asking just to be sure about this.

Cheers,
Mihai

Paul van Avesaath , 08-23-2019, 01:06 AM

matched is always better.. it allows the chip to absorb all other things that happen in your PCB. (timing wise)

ypkdani , 11-11-2019, 01:08 AM

Hello all,

i'm designing a pcb with an ethernet interface RMII with long nets from the mcu using altium. I have follow the advanced course of Fedevel so i have set the xsignal roules for length match and set the impendece to 50ohm. My question is about the signal MDIO and MDC, these signal need to be length matched respect the RX/TX/CLK signals or not?
I have put the resistences on the nets RX near the chip KSZ8081 and i will put the resistences near the mcu for the TX lines, is rigth?


Attached the image

Thanks

robertferanec , 11-11-2019, 06:20 AM

You can imagine MDIO and MDC basically like I2C. It is there just to configure registers inside of the chip. You do not have to length match it. More info https://en.wikipedia.org/wiki/Manage...a_Input/Output

You place series termination close to OUTPUT pins (some chips mark RX as output some use TX, so it depends how they mark the chip and pins). Also, series termination resistors are not always required.

ypkdani , 11-11-2019, 07:01 AM

Hi Robert,

for the KSZ8081 the datasheet say: TXD are transmit Data Input and RXD MII Receive Data Output so the design should be right.

Thanks for the information!!