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chitransh92 , 05-14-2019, 01:59 AM

Hello,

I am working with a board which is of 4 layers and with Signal-GND-Power-Signal layer arrangement.
Question is, will adding the GND polygons to the extra space that is left out on top/bottom layer after routing the traces helpful or not?

This board is based on "PIC32MX534F064HT-I/PT" PIC Controller which has a max frequency of 80MHz

Thank you.

Lakshmi , 05-14-2019, 03:02 AM

Yes, If you have space left on the Top n Bottom Layer it's good practice to add GND Plane(Shielding).

chitransh92 , 05-14-2019, 03:59 AM

@Lakshmi, I saw some designs with this technique.however, for the High speed signals the lower impedance path lies just below the signal trace in this case don't you think that additional GND plane will add some conflicts for the return path.

Lakshmi , 05-14-2019, 04:19 AM

Yeah I agree but if you look at the Reference Design by some of the companies(like TI etc.) You'll generally see that in top and Bottom Layer space will be covered by GND(Make sure these GND planes have via connected GND Layer by many via's).
I have designed Two Boards as of now, In my first board I didn't add GND Plane and In my second Board I have covered the left spaces by GND Planes Which is more stable.

Paul van Avesaath , 05-14-2019, 06:43 AM

keep in mind that in some cases filling an area with GND will get a gnd plane next to switching components and then you might get added noise on your gnd plane..
@Lakshmi, you cannot compare stability of to independed boards and contributing the stability towards GND planes..

chitransh92 , 05-14-2019, 07:12 AM

@Paul van Avesaath , I agree.
Hence in this case the area near switching components must be left as is if GND polygon is to be poured.

Paul van Avesaath , 05-14-2019, 07:40 AM

in this case i should not worrie about it... also you remark on the highspeed lines getting interference. they wont.. they will always take the path of least resistance. or in this case your GND plane

chitransh92 , 05-14-2019, 07:51 AM

@Paul van Avesaath Per my understanding for the high speed signal it is actually path will less "impedance" not only the resistance.
Also there is enough resource on the web to explain this phenomena.

This low impedance path is generally just below the signal trace, hence it is also advisable to have a ground/power plane below signal layer.
Going by this explanation if the signal layer is surrounded by by GND plane all over then it can affect the return path of the signal hampering the loop size.

In my opinion.
Share your thoughts. :-)

Paul van Avesaath , 05-14-2019, 01:12 PM

there is no path of less " impedance"...... impedance is a trace which is referenced either to another trace or a plane (distance). yes an impedance trace is usually referenced towards a GND plane, to make things easier to understand. but theoretical (and in practice) an impedance track can be referenced to a 12V power plane just as good or like in a differential trace the differential impedance totally different from the single trace impedance. Zodd and Zeven are also different al these calculation add up to what we callimpedance.. . its math not science and electrons. when I mentioned path of least resistance i meant that a return current will always try and flow beneath or along side the trace it will belong to. and it will always choose the path of least resistance.. and a GND plane is for the most part the least resistive of all in a system. even if you couple a top gnd plane with a zillion via's to the gnd plane beneath a trace,, it will always go below the trace

robertferanec , 05-15-2019, 02:12 AM

- I do not do it. I read somewhere (and it may be truth), if done wrong it can actually make your PCB worse, especially from EMC/EMI point of view. However, I have not really compared PCBs with / without GND flooding, so I do not have any real world example to say if it is good or wrong.

chitransh92 , 05-17-2019, 04:26 AM

Hello,
As per TI's app note "swra367a" they recommend to add the ground polygons to the left out space on top and bottom layer in section 3.5.
Also I would agree to @robertferanec's " if done wrong it can actually make your PCB worse".

I will update this thread in case i find some practical examples explain the scenario.

robertferanec , 05-20-2019, 02:51 AM

@chitransh92, yes, you need to know what you are doing e.g. they exactly tell you "... connect this top fill with the ground plane below with several vias. It is
recommended to have these vias spaced about 1/10th of the wavelength apart". This note is very important. However many people just flood GND between tracks and connect it with one VIA or they leave long parts of GND hanging around PCB making antennas.

So if a document describes what to do, then it is fine. If people are not sure how to do it properly, then it may be better not do it as it can really make the PCB worse.

Beko , 09-26-2020, 05:30 AM

Hi,

This may be an old post but I wanted to bring the topic live again after I watched Rick Hartley's video (https://resources.altium.com/p/indus...board-stack-up). Rick basically says that if you have good ref GND plane right under your signals, then you can contain the signal energy. So my first thought is, if I have a close GND plane to my signal plane, I do not need any GND fills on my signal layers. However he also recommends some stackups with GND+Signal layers and mentions GND fills briefly.

So I am confused, if you have a nice GND plane under your signal plane, can you still benefit from a GND fill on your empty areas in your signal plane? Any expert advice would be much appreciated.

Regards,

Beko

qdrives , 09-26-2020, 10:18 AM

I do not see any mentioning here for copper balancing. Both for the electroplating as for the wave soldering (if done).
I have always filled all layers with GND. There are a couple of things you also have to do:
- Remove small islands (automatically)
- Connect it with via's
- Put polygon pour cutouts there where you do not want the GND (like under an inductor of your SMPS)