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Didan , 04-03-2019, 04:15 PM

Dear forum, Im really stuck in a Qualcom Snapdragon Processor APQ8016 fanout, Kingston eMMC 5.1 HS400 fan out, PMIC8916 fanout and Wifi + Bluetooth + GPS fanout besides high speed interface as well on whole board... even I had took advanced layout course with iMX6 open rex project, had studied its iMX6 fanout, DDR3 fanout I dont have idea about how should I keep going on with this board. This project is a exactly copy based on Dragonboard410c, my company got all datasheets like dragonboard 410c schematic which I copied, I made all footprints for project and followed assembly drawing where indicate placement for components, what I think I did well too... Its a 12 layers board and i copied iMX6 stackup. there are lot of things to say about this project but being directly I ve been working on it for more than 2 months and finally finished placement and its time to route it. I started placing all GND Vias for whole board but I dont know any open hardwarece development board which use APQ8016, eMMC, PMIC8916 and modem GPS+Wifi+bluetooth. Problem here is because different from iMX6 which BGAs have a 0.8mm pitch between pads but regular distribution, APQ8016 doesnt. I wanna know if somebody here have any reference about open development board which use these guys that I need to fan out and if somebody should help me with this project. Moreover, my doubt is about figure gnd_apq8016, as APQ8016 pads are irregular, isnt linear, there are interleaved pads in diagonal and Im already using 0.1mm hole and 0.27 diameter via which is equivalent for "microvia on iMX6 project" and its already very very small, its right I make use for even smaller via like figure gnd_apq8016 for it fit between 4 pads, I needed to use 2.5 mil hole and 7 mil diameter via. Its right or its ok only use a polygon for this gnd corridor? its because from iMX6 I learned that we should use at least 1 via for 2 gnd pads, so im worrry about space here, via size and etc... If someone need more information let discuss about it, I really need help and recommendations for people who know very advanced layout for these kinds for ICs.

mairomaster , 04-04-2019, 06:22 AM

You haven't specified the most important parameter - what is the pitch of the device (pin to pin)? To me it pretty much looks like it's designed to be fanned out using via in pad. I wouldn't go any smaller than 0.275 mm uvia with 0.1 mm hole. Even with this some manufacturers might not be entirely happy, because of the small annular ring.

The advanced layout course gives you some good fundamentals and understanding in high speed layout design (I did it myself some years ago), but you need a lot of additional experience to be able to comfortably do some advanced boards.

Didan , 04-04-2019, 09:30 AM

Hi Mairo. I attached some prints for you check pitch

Paul van Avesaath , 04-04-2019, 02:05 PM

well you have certainly jumped into the deep here Didan.. with this design you will limit yourself very much on who can produce this type of PCB.
In your case you must find a manufacturer and ask them what they can make with a decent yield..
they will charge a pretty penny to produce this..

you are looking at multiple stages in micro via to internal via's and you are correct that power will become a struggle to comply with all factors.
you will most certainly have some trade-offs

I usually use 4mil/10mil for micro via, and 18/8mil for normal via's in my HDI design.
you can calculate the power it can sink or source through saturn PCB.

and I agree with @mairomaster that you probably are lookin at via in BGA pas


you might want to check if you are able to get the same chips in a bigger spaced package..that can save you on technology for production.
so if you are not that critically space restricted that would be the first step to look at.

also try and get hold of the schematic/ pcb gerbers from the devkits they usually show at least one way of doing things..

Paul van Avesaath , 04-04-2019, 03:10 PM

Hi Didan,

sorry i dont have any designs lying around that would help you here.
(btw if you want to clone a board it might be better to buy it is much cheaper )

I understand you want to learn, but in most cases it is done with trial and error. and that takes time,

go for it, but first make an appointment with your PCB manufacturer. or at least talk with a few to see what their capabilties are. they can assist you in what parameters (like via size / clearance) you can and should use. try and find the bigger packages if possible..

if you cant find the specific type of devkit try and look for others out there... like
https://www.xilinx.com/support/docum...sign-rules.pdf



with regards to the via power, just put your values into Saturn PCB tool and see how much current it can do for you.

hope this helps a bit
​

robertferanec , 04-08-2019, 01:54 AM

What could help, google for "0.4 mm pitch bga fanout". There is some good reading, for example the one recomended by @Paul van Avesaath : http://www.ti.com/lit/an/spraav1b/spraav1b.pdf
If you do not have any 0.4 boards, in the document above they refer to Beagleboard, you can download the files from here https://elinux.org/Beagleboard:Beagl...Hardware_Files

PS: The reference board of the processor what you are using should give you a good idea how to fanout the processor. Do you have access to the reference board?

Didan , 04-08-2019, 09:26 AM

@mairomaster what do you mean by via in pad? I didnt find any tutorial about it for me watch it and really understand. I really would like some help in here thanks for everyone sharing pdfs documents and infos ... I would like much more and I read some here, opened beagleboard on Allegro but didnt help me as I was expecting, but ok. Im waiting for more advices thanks

Paul van Avesaath , 04-08-2019, 03:14 PM

i think @mairomaster meant that you have via's in the BGA pads, you can do this but the via;s need to be filled in with copper and treated like a BGA pad.

Didan , 04-09-2019, 08:23 AM

someone here know how to create polygon for small areas? Like picture attached I couldnt repour small polygons and it looks work for bigger areas. How to modify, if there are these options, about polygon areas?

Paul van Avesaath , 04-09-2019, 08:28 AM

ask your PCB supplier for plugged via's and how they want you to specify these.. I used to add it in text in a mechanical layer with something like " all via's should be plugged and plated according to IPC" some number" then it is finished.. but again you should contact you pcb supplier to what standards yuou want this.. I can check later today on the exact ipc number it was done for me..

Paul van Avesaath , 04-09-2019, 08:31 AM

sometimes altium does this.. there is a reason for it but it has to do with some items in the rules i believe, you can also use a " fill" in some cases

mairomaster , 04-09-2019, 09:49 AM

Use fills and regions wherever possible. Polygons misbehave all the time and should only be used when necessary. With your example you can easily use fill/region instead. If you really need a polygon and it refuses to re-pour (after manually re-pouring it with the command repour selected/all), check it's properties. It must have the proper net assigned. I don't remember by heart but there are some settings about min neck size, min pour area and others. You might need to adjust those.

Didan , 04-09-2019, 10:59 AM

@mairomaster you told above polygons polygons should only be used when necessary, about PMIC fan out for this board I started discussion here, I've been doing what I think its right. All vias are microvias L1-L2 on pmic fanout as well eMMC memory. So about these fan out do you think it looks good and follow standard rules?

Paul van Avesaath , 04-09-2019, 12:34 PM

the text i used for plugged and plated via's was

All via's should be plugged and plated according IPC-4761 Type VII.

you will need to talk with your PCB manufacturer if they can comply with this..
I placed the tekst onto a mechanical layer. and reffered to it in my printspecification file.

just to make sure @Didan do or don't you know what PCB manufacturer you are going to use?
I can't stress enough that you need to have communications with them at this point in your project...
the faster you can get manufacturing involved the better off you will be.. (and i know what a pain in the ass manufacturers can be)

just look at it this way.. if you are done with your design you will be so happy you did..or else you might hear something like:
we can't do it like this.. you should have used this via or minimum trace width, or this stackup..
not all manufacturers can make every design you make, for most of us we learned the hard way

also think ahead about testing your board. if you can let your OEM do this you need to implement that from the start.

good luck and show us from time to time your progress!!

robertferanec , 04-12-2019, 01:50 AM

- I often design boards without special support from chip company (for example Freescale / NXP they refuse to talk to me ... we do not manufacture boards and I do not buy their chips, so they will not talk to me), however I do not design boards if there is no access to full documentation and software (you need to be able sign NDA and get access to a directory with all documents, software and tools for the chip). If you do not have full access to all documentation, you may keep having problems not only with HW development, but also during debugging, testing, software development., etc.

I learned at the beginning of my carrier - use only the chips with great documentation and support, avoid using chips with poor, bad or no documentation.

robertferanec , 04-12-2019, 01:56 AM

as @mairomaster mentioned, you may want to check polygons parameters, especially have a look at the parameters with words: "Remove ... Less than ...." ... try to make the numbers in these parameters smaller, that should help.

robertferanec , 04-18-2019, 08:33 AM

- Awesome!