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Advanced PCB Layout Course - Practice on PCIE during lesson 2

Luca , 03-08-2019, 10:37 AM
Good evening to everyone, i'm attending Advanced PCB Layout Course.
During lesson 3 i'm training with PCIE and other high speed interfaces.
What i've done is attached as PCIE_different.
In comparison with release layout (also attached) i've noticed that there are vias from L1 (start) to L12 (stop) but signals re-start from L9 instead L12.
If i've well understand this create a vias-on-stubs, is right? If yes could cause some trouble? You have take this choice for PCB cost reduction? Orr simply because make the routing possibile in less layers?
As you can see in my layout i've used micro-vias + buried vias instead full stack vias, are still correct?
Please, help me to understand better this point.
robertferanec , 03-11-2019, 02:52 AM
You are thinking right. In this case, there will be no problems - tested ... and also it was used same way in the reference designs (don't forget, even PCIE slots are through hole connectors and often they have signals connected on different layers - see the example in the video I attached at the end).

For very high speed interfaces (e.g. more than 5GHz) you really need to consider stub in VIA, but even then you may be able to go away with some stubs. However, when I am doing layout I do consider stubs in VIAs and if possible I try to find a combination between uVIAs, Buried VIAs, Through hole VIAs which will create minimum or no stub when high speed signals are routed.

PS: This may be interesting for you: https://youtu.be/DFZyMycu96I?t=196
Luca , 03-15-2019, 02:35 AM
Thanks for good reply and very nice video!
I'll continue with layout trying to avoid stub vias as much as possible.
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