USE DISCOUNT CODEEXPERT30TO SAVE $30 USD
input RLC filter of power supply
Moataz Beheta , 03-15-2022, 10:41 AM
Hi
In "Lesson 5: Schematic Design - Power Supply" video, it was mentioned that the input RLC filter should have a high cut-off frequency in Mhz.
why should it be in Mhz? why we don't set the cut-off frequency to, for example, 100kHz or smaller to prevent any noise like the filter of LDO regulator? I think that will make it more efficient to filter low and high frequency coming from USB port
another question:
before the inductor, there is another 1uF capacitor, why we added to RLC filter, and how did we calculate its value?
In "Lesson 5: Schematic Design - Power Supply" video, it was mentioned that the input RLC filter should have a high cut-off frequency in Mhz.
why should it be in Mhz? why we don't set the cut-off frequency to, for example, 100kHz or smaller to prevent any noise like the filter of LDO regulator? I think that will make it more efficient to filter low and high frequency coming from USB port
another question:
before the inductor, there is another 1uF capacitor, why we added to RLC filter, and how did we calculate its value?
ahernandez , 04-12-2022, 09:34 AM
I've got another question: how do you calculate de 10nH value to let 500mA of current pass by the filter?
Thank you.
Thank you.
arx , 10-08-2023, 05:56 AM
I'm currently going over this course and I'd like to know the answers to all the questions above as well 
This is what Phil says in the video (lesson 5):
- does it mean that if the input pi filter filtered everything except DC, the digital circuitry would not be able to work at all?
- how do we calculate or ballpark the cutoff frequency of the input pi filter that we need, considering our digital circuitry we're going to use?
- how do we choose the value of L?
I've been trying to google some sources that would deal with this, but so far unsuccessfully.
@phils-lab please, would you be willing to provide some sources or explanation for us? Thank you!
This is what Phil says in the video (lesson 5):
[06:55] For power supply filtering, we don't want to filter esentially at 2, or 20, or 100 or a kilohertz. We want to keep the cutoff frequency fairly high, essentially just eliminating or redamping very high frequency noise. (...)
[07:30] Particularly for high-speed digital circuitry, you want to perform minimum filtering required (for example to pass EMI testing and so forth), because transients drawn by the ICs will require high frequency currents and you don't want to damp them too much.
[07:30] Particularly for high-speed digital circuitry, you want to perform minimum filtering required (for example to pass EMI testing and so forth), because transients drawn by the ICs will require high frequency currents and you don't want to damp them too much.
- how do we calculate or ballpark the cutoff frequency of the input pi filter that we need, considering our digital circuitry we're going to use?
- how do we choose the value of L?
I've been trying to google some sources that would deal with this, but so far unsuccessfully.
@phils-lab please, would you be willing to provide some sources or explanation for us? Thank you!
phils-lab , 10-08-2023, 01:29 PM
Here are some things I consider when I look at (rail) filtering:
- Put 'placeholder' PI filters on any power input/output (i.e. from PCB to connector, or connector to PCB. For example, from USB connector power). Even if the series element is just a 0-Ohm resistor and the parallel caps are DNP to start off with. Then, when it comes to compliance testing and we find we are failing, for example, conducted emissions, we have pads in place already to be able to try out combinations of series/parallel elements that can suppress frequencies that we are failing at.
The reason for the very generalised statement of 'a couple MHz' is that for a power-supply input filter this is a starting point from experience. It can very well be that we don't need it (replace inductor with 0R), or as has been mentioned above, that we need to increase the filtering effectiveness (lower cutoff, more damping, ...). This will have to be determined with the manufactured board of a design. Sometimes we may need common-mode chokes instead, or other filter structures.
- The reason for a cap before and after the series element is that the PI filter is bidirectional (noise entering and exiting the PCB can be suppressed).
- Cap value at the connector should be sized based on maximum allowed inrush currents (e.g. USB limit is ~10uF at the connector) and bandwidth limits of the filter. Derating needs to be taken into account.
- PI filters can also be used to slow down edges and reduce harmonic content of signals at connector boundaries to help with EMI (should be cautiously used). More info on this in Keith Armstrong's (EMC expert) EMC book https://www.emcstandards.co.uk/emc-f...circuit-boards
- For analogue supplies, that feed analogue sections not requiring fast transients, series elements (resistors (given appropriately calculated V and I^2*R losses), inductors, beads) can be appropriate. For example, for audio, my cut-offs have been significantly lower than 20Hz and have had no issues (other than requiring large capacitances to keep the Rs low). You'll also typically find ferrites on digital IC's PLL power supply inputs, for example - the required parts are given in the datasheet.
- In contrast, on supply rails that go to digital logic (e.g. after buck/linear regulator to an MCU), no ferrites/inductor on digital supply rails should typically be used. There are of course exceptions which may be highlighted in datasheets and app notes. However, experimental/practical results may vary and you may not need these additional series elements.
- The problem with inductances/ferrites in power distribution network (PDN) is that they can cause resonances (in combination with traces, decoupling caps, etc.). In particular, for digital PDNs they also can be problematic as these elements raise the impedance at frequencies at which we may not want them to act. Simulation of a real PDN can be difficult without rather costly software.
- Additionally, with (high-speed) digital PDNs there is something known as the target impedance, where impedance seen between PSU to IC package pin needs to below certain values across certain frequency bands (https://www.zuken.com/en/wp-content/...dor-target.png). This then gives insight (with simulation) how much capacitance we need, how traces/planes need to be sized for inductance/capacitance/resistance properties, etc. Again, target impedance needs to be kept (very generally speaking) in the order of mOhms up to several hundered MHz for high-speed digital ICs. Ferrites in series would completely ruin that impedance across a range of frequencies (in addition to having a comparatively high DC resistance).
- Unless you have accurate models and can simulate your circuits EM behaviour. most of this will have to be experimental. It can very well be that you may not need line filtering in certain cases. I've also chatted to Keith Armstrong about this, and believe this is the 'general answer'.
For more information, I'd also suggest looking at work by Steve Sandler (previously also featured on Robert's channel) and the book by Eric Bogatin 'Signal and Power Integrity'.
- Put 'placeholder' PI filters on any power input/output (i.e. from PCB to connector, or connector to PCB. For example, from USB connector power). Even if the series element is just a 0-Ohm resistor and the parallel caps are DNP to start off with. Then, when it comes to compliance testing and we find we are failing, for example, conducted emissions, we have pads in place already to be able to try out combinations of series/parallel elements that can suppress frequencies that we are failing at.
The reason for the very generalised statement of 'a couple MHz' is that for a power-supply input filter this is a starting point from experience. It can very well be that we don't need it (replace inductor with 0R), or as has been mentioned above, that we need to increase the filtering effectiveness (lower cutoff, more damping, ...). This will have to be determined with the manufactured board of a design. Sometimes we may need common-mode chokes instead, or other filter structures.
- The reason for a cap before and after the series element is that the PI filter is bidirectional (noise entering and exiting the PCB can be suppressed).
- Cap value at the connector should be sized based on maximum allowed inrush currents (e.g. USB limit is ~10uF at the connector) and bandwidth limits of the filter. Derating needs to be taken into account.
- PI filters can also be used to slow down edges and reduce harmonic content of signals at connector boundaries to help with EMI (should be cautiously used). More info on this in Keith Armstrong's (EMC expert) EMC book https://www.emcstandards.co.uk/emc-f...circuit-boards
- For analogue supplies, that feed analogue sections not requiring fast transients, series elements (resistors (given appropriately calculated V and I^2*R losses), inductors, beads) can be appropriate. For example, for audio, my cut-offs have been significantly lower than 20Hz and have had no issues (other than requiring large capacitances to keep the Rs low). You'll also typically find ferrites on digital IC's PLL power supply inputs, for example - the required parts are given in the datasheet.
- In contrast, on supply rails that go to digital logic (e.g. after buck/linear regulator to an MCU), no ferrites/inductor on digital supply rails should typically be used. There are of course exceptions which may be highlighted in datasheets and app notes. However, experimental/practical results may vary and you may not need these additional series elements.
- The problem with inductances/ferrites in power distribution network (PDN) is that they can cause resonances (in combination with traces, decoupling caps, etc.). In particular, for digital PDNs they also can be problematic as these elements raise the impedance at frequencies at which we may not want them to act. Simulation of a real PDN can be difficult without rather costly software.
- Additionally, with (high-speed) digital PDNs there is something known as the target impedance, where impedance seen between PSU to IC package pin needs to below certain values across certain frequency bands (https://www.zuken.com/en/wp-content/...dor-target.png). This then gives insight (with simulation) how much capacitance we need, how traces/planes need to be sized for inductance/capacitance/resistance properties, etc. Again, target impedance needs to be kept (very generally speaking) in the order of mOhms up to several hundered MHz for high-speed digital ICs. Ferrites in series would completely ruin that impedance across a range of frequencies (in addition to having a comparatively high DC resistance).
- Unless you have accurate models and can simulate your circuits EM behaviour. most of this will have to be experimental. It can very well be that you may not need line filtering in certain cases. I've also chatted to Keith Armstrong about this, and believe this is the 'general answer'.
For more information, I'd also suggest looking at work by Steve Sandler (previously also featured on Robert's channel) and the book by Eric Bogatin 'Signal and Power Integrity'.
arx , 10-08-2023, 02:31 PM
Wow, thank you so much for all this wisdom, clarifications, notes and also the sources - I have much to go through now! Much appreciated!
phils-lab , 10-08-2023, 03:17 PM
You're very welcome - hope that helps!
Use our interactive Discord forum to reply or ask new questions.