FEDEVEL
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mulfycrowh , 05-05-2017, 09:53 AM

Hi everybody !

A question about implementation of DDR4.
I have downloaded a schematic from JEDEC website about SODIMM.
As you can see data bus do not match with data bus on ic.
For example, on U1, DQ0 comes with DQ01R, ..., DQ7 with DQ06R

Why such link ?

Thanks a lot.

mairomaster , 05-08-2017, 02:11 AM

My guess will be that they used pin swapping to ease the layout. There is a good amount of information on the topic on the web.

mulfycrowh , 05-08-2017, 03:19 PM

Thank you. It's a good explanation since order of data bus doesn't matter

mairomaster , 05-09-2017, 01:39 AM

Well, it's still important to be careful. With DDR3 many times you need at least the first bit in a byte to be directly connected (DQ0, DQ8, DQ16, etc.). That is required for calibration purposes. Sometimes you might need the last bit in a byte to be directly connected as well. It all should be mentioned in the documentation of the particular CPU.