FEDEVEL
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robertferanec , 07-29-2020, 03:43 AM

I am creating this post as a space for your stackups which you are happy to share with others. Feel free to upload here the stackups what you have used in your projects. It can really help to other people. Thank you for sharing. - Robert

robertferanec , 07-29-2020, 03:46 AM

And here is my contribution. All the stackups are based on my article here:
https://welldoneblog.fedevel.com/201...your-projects/

More information about these stackups can be found in this video:


6 Layers 1-6 - S55 D90 D100 - iMX6 Tiny Baseboard Lite V1I1.pdf
12 Layers 1-1-8-1-1 - S55 D90 D100 - Controled impedance on 6 layers - Computer on module 02.pdf
10 Layers 1-10 - S50 D90 D100 - Fedevel_OpenRex PCB V1I1_10L_VT47_v04.pdf
12 Layers 1-1-8-1-1 - S55 D90 D100 - iMX6_Rex_V1I1_PCB_12L_VT47_mv - in MM.pdf
12 Layers 1-1-8-1-1 - S55 D90 D100 - iMX6_Rex_V1I1_PCB_12L_VT47_mv - in MILS.pdf
12 Layers 1-1-8-1-1 - S47 S50 D72 D85 D90 D100 - Industrial Motherboard 01.pdf

giannisasp , 07-31-2020, 03:31 AM

Hi Robert,
Here is a small contribution from me as well.
Its a custom 6L stackup from an FPGA board with DDR2 that I designed some time ago. I have reused that stackup elsewhere as well.
I hope someone finds it usefull.
Giannis.

Armin , 08-18-2020, 06:37 AM

Hi dear Robert. I designed a 16 layer PCB. KU060 Xilinx FPGA with DDR4. I had 3G SDI with 75Ohm Impedance. I hope someday anyone can use.

milos.stankovic , 07-12-2022, 01:23 AM

Hi!
For 4L- board I used PWR/SIG at L1 and L4, with L2 and L3 as GNDs (one GND polygone or more, depending on number of GNDs). Guy from previous company suggested this stackup. Ric Hartley also mention it in https://www.youtube.com/watch?v=52fxuRGifLU with Robert. He mentioned that this stackup is good for digital boards, if I remember correctly. If there are sensitive tracks, they should be hidden inside the board, and with this stackup that is not possible.



Regards,
Miloš