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Platform forum

bossssie , 01-06-2021, 01:42 AM

Hi,

I am currently designing a board based on the i.mx6ull 14x14 evk and have selected a 1GB 16 bit memory chip (MT41K512M16HA-125). I have followed your video about simulating DDR3 in sigrity and it was really easy with this video.
The problem I have now with the simulation is that I have hold time violations for all the data lines. I think this is because the length of the data lines is shorter than the address and clock lines. I matched the DQ signal to the data byte. And all the other signals to the address and clock.
I think this should be able to be compensated by write leveling calibration, but I want to make sure this is the case. Is there any way to add write leveling to the simulation or do I have to calculate the timing manually?

Corné

robertferanec , 01-11-2021, 01:29 AM

- Data uses DQS as the strobe signal. I believe, they can be shorter than addr/cmd/ctl/ck and there should be no problem.

- I think, I have seen there an option to add write leveling. I do not have access to the tool right now, but I think I played with it. (or maybe was a different software? I do not remember)

PS: I have spent a lot of time trying to set the simulation the way that everything would pass, but for this you may need someone from Cadence to help you with it. Often you would need to set some other parameters e.g. which are based on memory controller register settings and it is not easy to replicate the simulation with the exact parameters which you will have have on your board. So, when I do memory simulation I often just have a look at signal quality and I ignore some other results.