OpenRex DDR3 Memory Interface - A14
schad.rio , 05-24-2018, 09:05 AM
On pg3. CPU DDR3, DDR3 Mem of the OpenRex schematic, I notice that pin A14 is not grouped with the other address input pins but instead with the NC pins. I understand the processor supports up to a 16 bit bus and this particular DRAM (256Meg x 16) supports up to 15 bits for the row addressing (see attachment). Why is pin A14 grouped separately from the other input pins and not labeled as an input ?
robertferanec , 05-24-2018, 09:53 PM
No special reason. The original symbol was for smaller memory and A14 was added later.
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