FEDEVEL
Platform forum

avion , 01-21-2018, 01:28 PM

I cant find any good explanation on rules for clock and data lines matching guidelines for high speed signals such as DDR3 and RGMII. In IMX6 rex DDR ram data bus should be -200mil shorter to ddr clocks. But there are no rules for RGMII anywhere... Is it right to assume that all synchronous transmission protocols should have clock always longer than data lines? Is there a book or source to learn more about this topic?

robertferanec , 01-21-2018, 09:34 PM

There is no general rule - you need to follow design guide. Each chip is build differently and sometimes they may include some length matching stuff inside the chip itself (e.g. I use chips where clock had to be longest, but I have also used chips where CMD/CTL/ADDR signals could be routed around clock).

RGMII layout may depend on version of RGMII which the chip is using (if I remember right, older version may require length adjustment on PCB, other version is doing this on silicon). Also, sometimes you can tune RGMII delay inside the chip (there are some registers). You can find some recommendations on google (e.g. try google for "rgmii layout guidelines"), but ideally is to follow design guide for your specific chip.

Generally, if I do length matching I almost always try to make the CLK the longest one in the group (unless it is otherwise specified).