OpenRex return path in DDR3 signals when reference plane is switched
diegopm , 04-04-2017, 09:58 AM
I am wondering about what happens when switching reference plane. For instance, in OpenRex board there is tracks that begin in L1 (ref plane L2) and change to L8 (ref plane L7 and L8) through via.
What’s happen with return path?
I think there are two options:
1) The return path is accomplished as a capacitive coupling between planes, but I think it is valid if the planes are close and the dielectric are thin.
2) The return path is lead to gnd vias (only GND planes, not fot L7 because is power plane). If we look at data lanes in OpenRex it could be an option because there are many GND connections near to signal vias in both CI (mem and micro). But, in address bus there are signal vias without nearest GND vias.
How we can improve the return path? Could be an option to put GND via near to every signal via when plane reference switch?
I put photos of two switching reference plane:
DRAM_A3 and GND L10 (microstrip refplane L9) to L3 (stripline refplane L2 and power plane ref L4)
CLK switch between L1 to L8
What’s happen with return path?
I think there are two options:
1) The return path is accomplished as a capacitive coupling between planes, but I think it is valid if the planes are close and the dielectric are thin.
2) The return path is lead to gnd vias (only GND planes, not fot L7 because is power plane). If we look at data lanes in OpenRex it could be an option because there are many GND connections near to signal vias in both CI (mem and micro). But, in address bus there are signal vias without nearest GND vias.
How we can improve the return path? Could be an option to put GND via near to every signal via when plane reference switch?
I put photos of two switching reference plane:
DRAM_A3 and GND L10 (microstrip refplane L9) to L3 (stripline refplane L2 and power plane ref L4)
CLK switch between L1 to L8
robertferanec , 04-04-2017, 10:52 AM
If there is space and if it is needed, then when you are changing GND reference planes, you may want to add stitching GND VIAs (a simple VIA connecting all the GND planes). Place it close to the place where signal is changing reference planes.
PS: sometimes, there is no space, so you rely on the GND VIAs around, e.g. GND VIAs used by decoupling capacitors.
PS: sometimes, there is no space, so you rely on the GND VIAs around, e.g. GND VIAs used by decoupling capacitors.
diegopm , 04-05-2017, 02:05 AM
Hi Robert,
Thanks you for your quick response
I am designing a imx6 system, so I am learning how to implement ddr3 bus.
Do you simulate the bus with HyperLynx or ADS or similar to validate the routing?
Thanks you for your quick response
I am designing a imx6 system, so I am learning how to implement ddr3 bus.
Do you simulate the bus with HyperLynx or ADS or similar to validate the routing?
robertferanec , 04-05-2017, 09:49 AM
We only simulate if we break too many rules. In that cases, I have used HyperLynx.
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