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Flashing A Custom Imx6Q Board for First Time
ranaya , 03-22-2017, 05:28 AM
Hi All,
I have a custom board based on IMX6 Rex layout. To give a fresh flash I want to add my RAM configurations to the uboot. Can some one explain how the ram configuration should be performed for a custom board ? Or can someone share the ram configuration file of iMX6 rex ?
I am using 4 RAM chips of AS4C256M16D3A-12BCN (256Mx16 each and 800Mhz) with the Rex layout. I tried setting these parameters in the ram script aid excel sheet, but can't find relevant fields for clock frequency ! Processor is IMX6Q
Thanks in Advance
I have a custom board based on IMX6 Rex layout. To give a fresh flash I want to add my RAM configurations to the uboot. Can some one explain how the ram configuration should be performed for a custom board ? Or can someone share the ram configuration file of iMX6 rex ?
I am using 4 RAM chips of AS4C256M16D3A-12BCN (256Mx16 each and 800Mhz) with the Rex layout. I tried setting these parameters in the ram script aid excel sheet, but can't find relevant fields for clock frequency ! Processor is IMX6Q
Thanks in Advance
robertferanec , 03-22-2017, 07:52 AM
@ranaya, you can find a lot of info on the imx6rex.com. This is for OpenRex, but it is very similar for iMX6Rex Module:
- You need to run calibration to get the values: http://www.imx6rex.com/software/how-...ation-on-imx6/
- Web: http://www.imx6rex.com/open-rex/soft...-custom-board/
- The file with memory controller values: mx6q_4x_mt41j256.cfg
Possibly, this could help you - it's an online course which I created for people to help to start with software for Rex projects:
- You need to run calibration to get the values: http://www.imx6rex.com/software/how-...ation-on-imx6/
- Web: http://www.imx6rex.com/open-rex/soft...-custom-board/
- The file with memory controller values: mx6q_4x_mt41j256.cfg
Possibly, this could help you - it's an online course which I created for people to help to start with software for Rex projects:
ranaya , 03-22-2017, 10:13 AM
Hi Robert,
thanks for your reply. One thing I need to understand. In order to get the Uboot console output, should I need to feed correct RAM configurations to Uboot sources ?
thanks for your reply. One thing I need to understand. In order to get the Uboot console output, should I need to feed correct RAM configurations to Uboot sources ?
ranaya , 03-22-2017, 10:59 AM
Hi, I have one question about DRAM clock frequency field of the aid xsl. Why it has only two frequencies 400 and 528MHz ? Does it mean that although my RAM has 800MHz rate, it has to somehow operate at one of those two frequencies ?
robertferanec , 03-22-2017, 06:02 PM
In order to get the Uboot console output, should I need to feed correct RAM configurations to Uboot sources ?
Why it has only two frequencies 400 and 528MHz ?
ranaya , 03-23-2017, 04:15 AM
Hi Robert,
Can you please kindly share the NXP DDR Test tool parameters and .inc file content with me ?
Can you please kindly share the NXP DDR Test tool parameters and .inc file content with me ?
ranaya , 03-23-2017, 04:25 AM
I am using imx6 rex board layout in my custom board and I am getting following error message in stress tester V2.6 :
The Ram chip I am using is :
http://www.alliancememory.com/pdf/dd...016%20v1.0.pdf
Any idea what causes this error ?
============================================
DDR Stress Test (2.6.0)
Build: Nov 18 2016, 23:40:32
NXP Semiconductors.
============================================
============================================
Chip ID
CHIP ID = i.MX6 Dual/Quad (0x63)
Internal Revision = TO1.2
============================================
============================================
Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00000000
SRC_SBMR2(0x020d801c) = 0x21000001
============================================
ARM Clock set to 1GHz
============================================
DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 64, bank num: 8
Row size: 15, col size: 10
Chip select CSD0 is used
Density per chip select: 2048MB
============================================
Current Temperature: 51
============================================
DDR Freq: 528 MHz
ddr_mr1=0x00000000
Start write leveling calibration...
running Write level HW calibration
Write leveling calibration completed, update the following registers in your initialization script
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x001F001F
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x001F001F
MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x001F001F
MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x001F001F
Write DQS delay result:
Write DQS0 delay: 31/256 CK
Write DQS1 delay: 31/256 CK
Write DQS2 delay: 31/256 CK
Write DQS3 delay: 31/256 CK
Write DQS4 delay: 31/256 CK
Write DQS5 delay: 31/256 CK
Write DQS6 delay: 31/256 CK
Write DQS7 delay: 31/256 CK
Starting DQS gating calibration
. HC_DEL=0x00000000 result[00]=0x11111111
. HC_DEL=0x00000001 result[01]=0x11111111
. HC_DEL=0x00000002 result[02]=0x11111111
. HC_DEL=0x00000003 result[03]=0x11111111
. HC_DEL=0x00000004 result[04]=0x11111111
. HC_DEL=0x00000005 result[05]=0x11111111
. HC_DEL=0x00000006 result[06]=0x11111111
. HC_DEL=0x00000007 result[07]=0x11111111
. HC_DEL=0x00000008 result[08]=0x11111111
. HC_DEL=0x00000009 result[09]=0x11111111
. HC_DEL=0x0000000A result[0A]=0x11111111
. HC_DEL=0x0000000B result[0B]=0x11111111
. HC_DEL=0x0000000C result[0C]=0x11111111
. HC_DEL=0x0000000D result[0D]=0x11111111
ERROR FOUND, we can't get suitable value !!!!
dram test fails for all values.
Error: failed during ddr calibration
The Ram chip I am using is :
http://www.alliancememory.com/pdf/dd...016%20v1.0.pdf
Any idea what causes this error ?
============================================
DDR Stress Test (2.6.0)
Build: Nov 18 2016, 23:40:32
NXP Semiconductors.
============================================
============================================
Chip ID
CHIP ID = i.MX6 Dual/Quad (0x63)
Internal Revision = TO1.2
============================================
============================================
Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00000000
SRC_SBMR2(0x020d801c) = 0x21000001
============================================
ARM Clock set to 1GHz
============================================
DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 64, bank num: 8
Row size: 15, col size: 10
Chip select CSD0 is used
Density per chip select: 2048MB
============================================
Current Temperature: 51
============================================
DDR Freq: 528 MHz
ddr_mr1=0x00000000
Start write leveling calibration...
running Write level HW calibration
Write leveling calibration completed, update the following registers in your initialization script
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x001F001F
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x001F001F
MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x001F001F
MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x001F001F
Write DQS delay result:
Write DQS0 delay: 31/256 CK
Write DQS1 delay: 31/256 CK
Write DQS2 delay: 31/256 CK
Write DQS3 delay: 31/256 CK
Write DQS4 delay: 31/256 CK
Write DQS5 delay: 31/256 CK
Write DQS6 delay: 31/256 CK
Write DQS7 delay: 31/256 CK
Starting DQS gating calibration
. HC_DEL=0x00000000 result[00]=0x11111111
. HC_DEL=0x00000001 result[01]=0x11111111
. HC_DEL=0x00000002 result[02]=0x11111111
. HC_DEL=0x00000003 result[03]=0x11111111
. HC_DEL=0x00000004 result[04]=0x11111111
. HC_DEL=0x00000005 result[05]=0x11111111
. HC_DEL=0x00000006 result[06]=0x11111111
. HC_DEL=0x00000007 result[07]=0x11111111
. HC_DEL=0x00000008 result[08]=0x11111111
. HC_DEL=0x00000009 result[09]=0x11111111
. HC_DEL=0x0000000A result[0A]=0x11111111
. HC_DEL=0x0000000B result[0B]=0x11111111
. HC_DEL=0x0000000C result[0C]=0x11111111
. HC_DEL=0x0000000D result[0D]=0x11111111
ERROR FOUND, we can't get suitable value !!!!
dram test fails for all values.
Error: failed during ddr calibration
robertferanec , 03-23-2017, 10:45 AM
I do not use V2.6. The log output looks weird to me. This is what we used in DDR Stress Tester V1.0.2 (2GB iMX6 Rex module - but I am not sure if this is the final file, this is what I found in my directory):
Code:
//============================================================================= //init script for i.MX6Q DDR3 //============================================================================= // Revision History // v01 //============================================================================= wait = on //============================================================================= // Disable WDOG //============================================================================= //setmem /16 0x020bc000 = 0x30 //============================================================================= // Enable all clocks (they are disabled by ROM code) //============================================================================= setmem /32 0x020c4068 = 0xffffffff setmem /32 0x020c406c = 0xffffffff setmem /32 0x020c4070 = 0xffffffff setmem /32 0x020c4074 = 0xffffffff setmem /32 0x020c4078 = 0xffffffff setmem /32 0x020c407c = 0xffffffff setmem /32 0x020c4080 = 0xffffffff setmem /32 0x020c4084 = 0xffffffff //============================================================================= // IOMUX //============================================================================= //DDR IO TYPE: setmem /32 0x020e0798 = 0x000C0000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPEsetmem /32 0x020e0758 = 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE //CLOCK: setmem /32 0x020e0588 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0setmem /32 0x020e0594 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 //ADDRESS: setmem /32 0x020e056c = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CASsetmem /32 0x020e0578 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RASsetmem /32 0x020e074c = 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS //CONTROL: setmem /32 0x020e057c = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET setmem /32 0x020e058c = 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDSsetmem /32 0x020e059c = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0setmem /32 0x020e05a0 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1setmem /32 0x020e078c = 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS //DATA STROBE: setmem /32 0x020e0750 = 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL setmem /32 0x020e05a8 = 0x00000028 //* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0setmem /32 0x020e05b0 = 0x00000028 //* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1setmem /32 0x020e0524 = 0x00000028 //* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2setmem /32 0x020e051c = 0x00000028 //* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3setmem /32 0x020e0518 = 0x00000028 //* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4setmem /32 0x020e050c = 0x00000028 //* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5setmem /32 0x020e05b8 = 0x00000028 //* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6setmem /32 0x020e05c0 = 0x00000028 //* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 //DATA: setmem /32 0x020e0774 = 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE setmem /32 0x020e0784 = 0x00000028 //* IOMUXC_SW_PAD_CTL_GRP_B0DSsetmem /32 0x020e0788 = 0x00000028 //* IOMUXC_SW_PAD_CTL_GRP_B1DSsetmem /32 0x020e0794 = 0x00000028 //* IOMUXC_SW_PAD_CTL_GRP_B2DSsetmem /32 0x020e079c = 0x00000028 //* IOMUXC_SW_PAD_CTL_GRP_B3DSsetmem /32 0x020e07a0 = 0x00000028 //* IOMUXC_SW_PAD_CTL_GRP_B4DSsetmem /32 0x020e07a4 = 0x00000028 //* IOMUXC_SW_PAD_CTL_GRP_B5DSsetmem /32 0x020e07a8 = 0x00000028 //* IOMUXC_SW_PAD_CTL_GRP_B6DSsetmem /32 0x020e0748 = 0x00000028 //* IOMUXC_SW_PAD_CTL_GRP_B7DS setmem /32 0x020e05ac = 0x00000028 //* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0setmem /32 0x020e05b4 = 0x00000028 //* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1setmem /32 0x020e0528 = 0x00000028 //* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2setmem /32 0x020e0520 = 0x00000028 //* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3setmem /32 0x020e0514 = 0x00000028 //* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4setmem /32 0x020e0510 = 0x00000028 //* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5setmem /32 0x020e05bc = 0x00000028 //* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6setmem /32 0x020e05c4 = 0x00000028 //* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 //============================================================================= // DDR Controller Registers //============================================================================= // Manufacturer: Micron // Device Part Number: MT41J128M16HA-15E // Clock Freq.: 533MHz // Density per CS in Gb: 8 // Chip Selects used: 1 // Number of Banks: 8 // Row address: 14 // Column address: 10 // Data bus width 64 //============================================================================= setmem /32 0x021b0800 = 0xa1390003 // DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration. // write leveling, based on Freescale board layout and T topology // For target board, may need to run write leveling calibration // to fine tune these settings // If target board does not use T topology, then these registers // should either be cleared or write leveling calibration can be run setmem /32 0x021b080c = 0x0013001F setmem /32 0x021b0810 = 0x00230011 setmem /32 0x021b480c = 0x0017001F setmem /32 0x021b4810 = 0x000E001D //###################################################### //calibration values based on calibration compare of 0x00ffff00: //Note, these calibration values are based on Freescale's board //May need to run calibration on target board to fine tune these //###################################################### //Read DQS Gating calibration setmem /32 0x021b083c = 0x432C0328 // MPDGCTRL0 PHY0setmem /32 0x021b0840 = 0x03240328 // MPDGCTRL1 PHY0setmem /32 0x021b483c = 0x432C033C // MPDGCTRL0 PHY1setmem /32 0x021b4840 = 0x03200268 // MPDGCTRL1 PHY1 //Read calibration setmem /32 0x021b0848 = 0x3A2E3234 // MPRDDLCTL PHY0setmem /32 0x021b4848 = 0x34322A3A // MPRDDLCTL PHY1 //Write calibration setmem /32 0x021b0850 = 0x3C3C4242 // MPWRDLCTL PHY0setmem /32 0x021b4850 = 0x42344438 // MPWRDLCTL PHY1 //read data bit delay: (3 is the reccommended default value, although out of reset value is 0): setmem /32 0x021b081c = 0x33333333 // DDR_PHY_P0_MPREDQBY0DL3setmem /32 0x021b0820 = 0x33333333 // DDR_PHY_P0_MPREDQBY1DL3setmem /32 0x021b0824 = 0x33333333 // DDR_PHY_P0_MPREDQBY2DL3setmem /32 0x021b0828 = 0x33333333 // DDR_PHY_P0_MPREDQBY3DL3setmem /32 0x021b481c = 0x33333333 // DDR_PHY_P1_MPREDQBY0DL3setmem /32 0x021b4820 = 0x33333333 // DDR_PHY_P1_MPREDQBY1DL3setmem /32 0x021b4824 = 0x33333333 // DDR_PHY_P1_MPREDQBY2DL3setmem /32 0x021b4828 = 0x33333333 // DDR_PHY_P1_MPREDQBY3DL3 //For i.mx6qd parts of versions A & B (v1.0, v1.1), uncomment the following lines. For version C (v1.2), keep commented //setmem /32 0x021b08c0 = 0x24911492 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6//setmem /32 0x021b48c0 = 0x24911492 // Complete calibration by forced measurement: setmem /32 0x021b08b8 = 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msrsetmem /32 0x021b48b8 = 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr //MMDC init: setmem /32 0x021b0004 = 0x00020036 // MMDC0_MDPDCsetmem /32 0x021b0008 = 0x09444040 // MMDC0_MDOTCsetmem /32 0x021b000c = 0x8A8F7955 // MMDC0_MDCFG0setmem /32 0x021b0010 = 0xFF328F64 // MMDC0_MDCFG1setmem /32 0x021b0014 = 0x01FF00DB // MMDC0_MDCFG2setmem /32 0x021b0018 = 0x00001740 // MMDC0_MDMISC//NOTE about MDMISC RALAT: //MDMISC: RALAT kept to the high level of 5 to ensure stable operation at 528MHz. //MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits: //a. better operation at low frequency //b. Small performence improvment setmem /32 0x021b001c = 0x00008000 // MMDC0_MDSCR, set the Configuration request bit during MMDC set upsetmem /32 0x021b002c = 0x000026d2 // MMDC0_MDRWD; recommend to maintain the default valuessetmem /32 0x021b0030 = 0x008F1023 // MMDC0_MDORsetmem /32 0x021b0040 = 0x00000047 // CS0_END setmem /32 0x021b0000 = 0x841A0000 // MMDC0_MDCTL // Mode register writes setmem /32 0x021b001c = 0x04088032 // MMDC0_MDSCR, MR2 write, CS0setmem /32 0x021b001c = 0x00008033 // MMDC0_MDSCR, MR3 write, CS0setmem /32 0x021b001c = 0x00048031 // MMDC0_MDSCR, MR1 write, CS0setmem /32 0x021b001c = 0x09408030 // MMDC0_MDSCR, MR0 write, CS0setmem /32 0x021b001c = 0x04008040 // MMDC0_MDSCR, ZQ calibration command sent to device on CS0 //setmem /32 0x021b001c = 0x0408803A // MMDC0_MDSCR, MR2 write, CS1//setmem /32 0x021b001c = 0x0000803B // MMDC0_MDSCR, MR3 write, CS1//setmem /32 0x021b001c = 0x00048039 // MMDC0_MDSCR, MR1 write, CS1//setmem /32 0x021b001c = 0x09408038 // MMDC0_MDSCR, MR0 write, CS1//setmem /32 0x021b001c = 0x04008048 // MMDC0_MDSCR, ZQ calibration command sent to device on CS1 setmem /32 0x021b0020 = 0x00005800 // MMDC0_MDREF // It is recommended for new board designs and for customer boards // to program these registers to a value of "0x00011117" // The DRAM ODT remains enabled and it is required to leave the DRAM ODT enabled setmem /32 0x021b0818 = 0x00011117 // DDR_PHY_P0_MPODTCTRLsetmem /32 0x021b4818 = 0x00011117 // DDR_PHY_P1_MPODTCTRL setmem /32 0x021b0004 = 0x00025576 // MMDC0_MDPDC with PWDT bits setsetmem /32 0x021b0404 = 0x00011006 // MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached. setmem /32 0x021b001c = 0x00000000 // MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)
ranaya , 03-23-2017, 10:17 PM
Thanks very much Robert, I appreciate your help. I'll give it a try with V1.0.2 ! I still have few confusions, now in our RAM chip,
1. We have 15 Row addresses (A[0:14]) and in schematic and layout DRAM_A14 (Pin T7) however is connected to processor DRAM_A14 (even A15 is available in schematic, I guess this is to easily extend different RAM chips ?). So should this be specifically mentioned in .inc file ? Or just mentioning 15 row addresses in aid.xlxs generates sufficient information for .inc file.
2. In the DQL aid xsls, we have only 400 and 528MHz frequencies. Why it has become 533MHz in your script ? Can you also point out the aid xslx you used for this RAM ?
3. I found a descrepncy in pin arrangement between SabreSD and OpenRex RAM connections. Specifically DQMx pins and Data pins were swapped. So If I can get your xsls aid script, that would give me correct script for RAM
1. We have 15 Row addresses (A[0:14]) and in schematic and layout DRAM_A14 (Pin T7) however is connected to processor DRAM_A14 (even A15 is available in schematic, I guess this is to easily extend different RAM chips ?). So should this be specifically mentioned in .inc file ? Or just mentioning 15 row addresses in aid.xlxs generates sufficient information for .inc file.
2. In the DQL aid xsls, we have only 400 and 528MHz frequencies. Why it has become 533MHz in your script ? Can you also point out the aid xslx you used for this RAM ?
3. I found a descrepncy in pin arrangement between SabreSD and OpenRex RAM connections. Specifically DQMx pins and Data pins were swapped. So If I can get your xsls aid script, that would give me correct script for RAM
ranaya , 03-24-2017, 03:57 AM
Hi, tried V1.0.2 version too. Same result found, except the V2.6 is bit more informative. Anyway I'm looking forward to hear from......................
robertferanec , 03-24-2017, 12:47 PM
I simply used the SD Sabre script file, run it on iMX6 Rex module and adjusted the values based on calibration results. That is what you can try too - it should give you some results and then you can continue by adjusting the script file.
1) using / not using A15 depends on what is the memory chip size which you fit on the board. Memory size is setup in the inc file - one of the registers. if your memory size is same as in the script file, you do not need to worry about it.
2) read the document included with the test tool. I think they explain it somewhere - I think the real frequency is 528
3) it doesn't influence the script file.
1) using / not using A15 depends on what is the memory chip size which you fit on the board. Memory size is setup in the inc file - one of the registers. if your memory size is same as in the script file, you do not need to worry about it.
2) read the document included with the test tool. I think they explain it somewhere - I think the real frequency is 528
3) it doesn't influence the script file.
ranaya , 03-26-2017, 09:54 PM
Hi, I am sure I put the correct memory information to the aid xsl, so the script file should be okay. Moreover I was able to run this on OpenRex board without any trouble. In our custom board, every time the calibration screwed up in DQS gating stage. Can't do stress test either. So would this be due to a layout issue ? The only change we made from Rex layout was adding an additional copper area to layer 3 and 10 (kindly take a look at pg1 and 2 attachments). Differential impedance was 100 ohm.
Moreover voltages levels seem to be correct and exactly what I expected (1.5V and 0.75 Vref).
What else we could count for our check list ?
Thanks in Advance
Moreover voltages levels seem to be correct and exactly what I expected (1.5V and 0.75 Vref).
What else we could count for our check list ?
Thanks in Advance
ranaya , 03-27-2017, 01:35 AM
Hi, one more thing, do you remember the delays reported for DQS and Data signals ? I'm trying to update MMDC_MPWLDECTRL0 register values to see whether I can make pass through ZDQ calibration.
Anuradha
Anuradha
robertferanec , 03-27-2017, 03:32 PM
@ranaya, try to run the memory calibration on your iMX6 Rex module. I do not have iMX6 Rex module with me. You can see an example of the calibration log output here: http://www.imx6rex.com/software/how-...ation-on-imx6/
ranaya , 03-30-2017, 03:58 AM
Hi Robert,
found the issue, the LVDS 2.5V supply was not provided to the custom board as I didn't intend to use LVDS. But found out that DDR3 shares LVDS power rails.
Thanks alot for your helps and suggestions.
Anuradha
found the issue, the LVDS 2.5V supply was not provided to the custom board as I didn't intend to use LVDS. But found out that DDR3 shares LVDS power rails.
Thanks alot for your helps and suggestions.
Anuradha
robertferanec , 03-30-2017, 07:13 AM
Thank you very much for sharing this.
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