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ADV7611 Linux Driver for IMX6Q

ranaya , 12-06-2016, 10:10 PM
Hi All, I am new to this forum and I hope this topic is relevant to this specific forum section.
I am implementing a custom board based around IMX6Q SoC and referred the open source rex project as an example. In one of Fedevel blog posts I saw an HDMI camera input being used, with aid of ADV7610 decoder chip. I plan to use ADV7611 instead and was wondering whether you have a supporting driver for it. or atleast I presume 7610 driver should work with 7611 too !

This is post I am referring to :

According to this, just installing mxc_v4l2_capture as a module seems to be enough to get the chip work. Does it mean that it can work standalone without any driver ?

Thanks in Advance
robertferanec , 12-07-2016, 10:09 AM
ranaya , 12-14-2016, 02:51 AM
Dear Robert, thanks for providing the helpful resources. Since the reg map of ADV7611 is pretty much same to t610, I think the driver should work with device tree binding !
ranaya , 01-23-2017, 10:56 PM
Dear robert, I came across a compilation error while adding adv7610.c file to the kernel. The compilation says 'V4L2_IDENT_ADV7610 undeclared (first use in this function)', where is this macro exactly defined in ?

It is similarly here in full driver :

Thanks in Advance
robertferanec , 01-24-2017, 12:23 PM
Honestly? I do not know. Try to search for it in the original source code.
ranaya , 01-24-2017, 08:47 PM
Hm.... may be it should be defined here, but no entry of it :

Couldn't spot the macro inside kernel repo too. According to what's given here, this can be written in same way as V4L2_IDENT_ADV7343 = 7343 !
Btw Robert, does this driver only support 8 bit and 16 bit modes interfaces ? I was wondering whether I can add 12-Bit SDR ITU-R BT.656 mode too to it. Thanks

robertferanec , 01-25-2017, 08:55 AM
Go through the part of the code with register settings. I do not remember exactly, but I think you can switch between any modes you need.
ranaya , 01-26-2017, 04:13 AM
Dear Robert,

Hi, I was able to compile the driver and loaded successfully to my system. I've made one change to the driver, commented 'define USE_16BIT' as I am trying to connect the chip in 8 bit mode (though I have settings in dtsi for 16bit). These are my observations :

lsmod | grep adv7610
adv7610_video 16384 0
v4l2_int_device 16384 4 ov5640_camera_mipi_int,tc358743_h2c_bridge,adv7610 _video,mxc_v4l2_capture

But when the kernel loads, these are the kernel prints :

- mxc_v4l_open: Mxc Camera no sensor ipu0/csi1
- mxc_v4l_open: Mxc Camera no sensor ipu0/csi0
- mxc_v4l_open: Mxc Camera no sensor ipu1/csi1
- ipu_csi_window_size_crop: Error left=0 top=59565955
- imx-ipuv3 2400000.ipu: Unsupported CCIR656 interlaced video mode

Unsupported CCIR656 should come from drivers/gpu/ipu-v3/ipu-csi.c file. What actually causes this issue ? Moreover these are my HW settings :

&i2c3 {    clock-frequency = <100000>;    pinctrl-names = "default";    pinctrl-0 = <&pinctrl_i2c3>;    status = "okay";    adv7610: adv7610@4C {          compatible = "adv,adv7610";          reg = <0x4C>;          pinctrl-names = "default";          pinctrl-0 = <&pinctrl_ipu1_csi0>;          csi_id = <0>;          ipu_id = <0>;          reset-gpio = GP_OV5642_RESET;   };pinctrl_ipu1_csi0: ipu1csi0grp {        fsl,pins = <            MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08        0x1b0b0            MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09        0x1b0b0            MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10        0x1b0b0            MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11        0x1b0b0            MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12        0x1b0b0            MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13        0x1b0b0            MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14        0x1b0b0            MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15        0x1b0b0            MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16        0x1b0b0            MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17        0x1b0b0            MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18        0x1b0b0            MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19        0x1b0b0            MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN    0x1b0b0            MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK    0x1b0b0            MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC        0x1b0b0            MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC        0x1b0b0            MX6QDL_PAD_GPIO_3__CCM_CLKO2            0x000b0        #define GP_OV5642_POWER_DOWN    <&gpio3 29 GPIO_ACTIVE_HIGH>            MX6QDL_PAD_EIM_D29__GPIO3_IO29            0x0b0b0#define GP_OV5642_RESET        <&gpio1 4 GPIO_ACTIVE_LOW>            MX6QDL_PAD_GPIO_4__GPIO1_IO04            0x030b0        >;};v4l2_cap_0 {        compatible = "fsl,imx6q-v4l2-capture";        ipu_id = <0>;        csi_id = <0>;        mclk_source = <0>;        status = "okay";    };    v4l2_cap_1: v4l2_cap_1 {        compatible = "fsl,imx6q-v4l2-capture";        ipu_id = <0>;        csi_id = <1>;        mipi_camera = <1>;        mclk_source = <0>;        status = "okay";    };    v4l2_cap_2: v4l2_cap_2 {        compatible = "fsl,imx6q-v4l2-capture";        ipu_id = <0>;        csi_id = <1>;        mclk_source = <0>;        status = "okay";    };    v4l2_cap_3: v4l2_cap_3 {        compatible = "fsl,imx6q-v4l2-capture";        ipu_id = <0>;        csi_id = <0>;        mipi_camera = <1>;        mclk_source = <0>;        status = "okay";    };

Thanks in Advance
robertferanec , 01-26-2017, 12:11 PM
Congratulation. This is some progress.

About specific issues - you will need to keep trying. I know it took us quite a while to figure out the correct settings. There are several different files used during the image processing, you may need to have a look into all of them to understand how it works.

Please, do not take it, that I do not want to help. I just do not remember - it was quite complicated. Even the final solution didn't come up from me - friend of mine found out what the problem was (it was something related to the kernel or filesystem). But we had a different kind of problem, it was something with interrupt and we were stacked on that problem for couple of weeks.
ranaya , 02-01-2017, 10:47 PM
Hi Robert, just want to let you know that, I was able to make some progress on this interfacing thing. Now I can see the device registration in kernel log :

mxc_v4l2_master_attach: ipu0:/csi0 parallel attached adv7610-video:mxc_v4l2_cap0

Now I can take the chip to free run mode, but in most of the time, the free run window crashes returning :

ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0
ERROR: v4l2 capture: unsupported ioctrl!

dqueue timeout thing need to be resolved. I am just updating this post, probably be useful for someone else in future.

ranaya , 02-02-2017, 02:44 AM
Btw were you able to get different color windows in free run mode ? I am trying to change the settings in addresses : C0,C1 and C2 to confirm it !
robertferanec , 02-04-2017, 09:59 AM
ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0
This is exactly the problem which I was getting, could not figure out how to fix it and friend of mine fixed it.

Btw were you able to get different color windows in free run mode
I have never played with these
ranaya , 06-02-2017, 03:42 AM
Dear Robert,

Hi, thought to write you to report another issue. I managed to get the chip running in 16bit free run mode as well (on openrex max board). However for an hdmi input signal from a camera, the chip cannot lock into the hdmi input signal. The driver reports "ADV7610 DE regen filter no lock" error and pushed the chip to free run mode. So I'd like to get review the ADV7610 schematic from you. If you do not mind can you share the schematic of working adv7610 chip ? Particularly I have a question about I2C2_DDC_SCL and SDA signals. in baseboard schematic, those signals are shown in attached pdf.

1. In that pdf can you kindly tell me how R6-R7 and R8-R9 should be arranged to properly work in HDMI input mode (let's say 720P) ?
2. According to your opinion what could cause this DE regeneration issue ?

Thanks in advance

Best Regards
robertferanec , 06-02-2017, 11:31 AM
1. I do not remember exactly, but I think ADV chip may be able to handle DDC by itself. You may also use software through I2C2 to read info about connected device to be able to set the correct resolution. However, I do not know exactly how it is handled - for the tests we did we only used fixed resolution. We never needed to support different HDMI devices and switch between resolutions automatically. But as it is, you should be able to read DDC info about the connected device and use software to set the correct resolution. That is only my theory.

2. I am not sure what mean by DE regeneration issue. Please, could you be more specific?
ranaya , 06-03-2017, 08:10 AM
I am referring to the following video :
I hope you will like TinyRex HDMI input interface. You can connect there any HDMI output (e.g. GoPro, Settopbox, PC ....) and process the video or transfer i...

1. But here the tinyRex is used for the HDMI camera. I think it is used with a Base Board right (tinyRex does not have HDMI chip, it connects to the HDMI through Base Board) ? So here if you can share the adv7610 input side schematic, I'd be able to take an idea. Since 16-Bit free run is working, I am sure from chip to imx6, the hardware works. Unknown part is the hardware between hdmi input port to chip !

2. DE Regeneration is related to HDMI input signal locking. This error appears because the chip cannot lock into HDMI input signal. So I want to make sure whether this happens because of hardware or software issue. Can you kindly take a look at the attached pdf and tell me, how those resistors are arranged in actual layout ?

robertferanec , 06-03-2017, 09:54 AM
1. That is the schematic which is on the website (I believe you have this one): http://www.imx6rex.com/wp-content/up...-Schematic.pdf

2. You can find all information about the TinyRex baseboard on the iMX6 Rex website - including BOMs and Layout. But I believe they are fitted (if they were not fitted, there would be NF text). HOwever you may want to compare it with BOM: http://www.imx6rex.com/downloads/
ranaya , 07-27-2017, 04:20 AM
Hi Robert, I managed to get the hdmi encoder to work. It works well for 720p and 1080p. The issue was in my EMI chip connections. Assuming it to be a pass through IC I hadn't routed the connections between each TMDS IN and OUT differential signal. So that encoder cannot lock-in to the TMDS clock and hence reporting "DE Regeneration Issue". Now it works. You can make this thread "SOLVED" Thanks for the support !!!

robertferanec , 07-27-2017, 04:57 AM
This is AWESOME!!! Thanks for letting us know.
ranaya , 08-09-2017, 05:46 AM
Hi Robert, I ran into the same mxc_v4l_dqueue timeout enc_counter 0, when trying this with an IMX6 custom board, but utilizing IPU1_CSI0 interface. That's the only difference I see between OpenRex (IPU2CSI1) board and this custom (IPU1_CSI0) one. If you do not mind can you kindly point me the person who solved this issue for you ?

robertferanec , 08-09-2017, 09:57 AM
I asked him for help. However, he is very busy and because it was some time ago, even he may not remember exactly what the solution was. Let's see ..
ranaya , 08-10-2017, 12:31 AM
Thanks, awaiting your response too. If it was added as a commit then would be easier to find it in git repo. Do you remember you've done something like that ?

Btw I saw the structure of mxc_v4l2_capture.c of Rex kernel is bit different to the one I am work on (it's from boudnary devices). I did some modifications to the file according to Rex, but the errors seems to be appearing ! Was that a HW change you guys did to overcome the issue ?


robertferanec , 08-11-2017, 09:33 AM
This is answer from the friend of mine. It was long time ago, so I hope at least this can help:
RE the error: I don't know the exact solution to the problem, but you can find the working driver here: https://github.com/OpenSolo/imx6-lin...ture/adv7610.c
ranaya , 08-18-2017, 04:36 AM
Hi, finally solved the issue. The workaround was some DTB changes. I figured out that for the IPU1_CSI0, the pin mux configuration values should be different (1b0b0) as their register bit arrangement (so properties) is different to IPU2_CSI1. Btw have you ever got interlace hdmi input modes captured with this ? Now I am working on that, I was wondering whether by changing only the EDID settings we would be able to do that, wouldn't we ?

robertferanec , 08-18-2017, 11:05 AM
Honestly I have no idea. I am the hardware guy. We very often design HW and build the SW which is able to test it. We usually do not work on further SW development
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