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&i2c3 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; adv7610: adv7610@4C { compatible = "adv,adv7610"; reg = <0x4C>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ipu1_csi0>; csi_id = <0>; ipu_id = <0>; reset-gpio = GP_OV5642_RESET; };pinctrl_ipu1_csi0: ipu1csi0grp { fsl,pins = < MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0 MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0 MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0 MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 #define GP_OV5642_POWER_DOWN <&gpio3 29 GPIO_ACTIVE_HIGH> MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0b0b0#define GP_OV5642_RESET <&gpio1 4 GPIO_ACTIVE_LOW> MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x030b0 >;};v4l2_cap_0 { compatible = "fsl,imx6q-v4l2-capture"; ipu_id = <0>; csi_id = <0>; mclk_source = <0>; status = "okay"; }; v4l2_cap_1: v4l2_cap_1 { compatible = "fsl,imx6q-v4l2-capture"; ipu_id = <0>; csi_id = <1>; mipi_camera = <1>; mclk_source = <0>; status = "okay"; }; v4l2_cap_2: v4l2_cap_2 { compatible = "fsl,imx6q-v4l2-capture"; ipu_id = <0>; csi_id = <1>; mclk_source = <0>; status = "okay"; }; v4l2_cap_3: v4l2_cap_3 { compatible = "fsl,imx6q-v4l2-capture"; ipu_id = <0>; csi_id = <0>; mipi_camera = <1>; mclk_source = <0>; status = "okay"; };