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Current Carrying Capability of a Via with No Clearance
abarnai , 09-28-2016, 12:52 PM
Advanced PCB Layout Course - Online, Lesson 3, about 35 minutes into the video, Robert is explaining using the Saturn PCB toolkit for determining current carrying capability of a via. We are using the Clearance Design Rule setting in Altium for a via, with the clearance value around the via.
Actually where you apply it there is no clearance to copper around the via.
Are you using it this way, because the Saturn PCB toolkit doesn't have provisions otherwise, with vias with no clearance to copper?
(Obviously, a via with copper all around will carry more current, so I guess you cannot go wrong with calculating with clearance)
See screen shot from video.
Thanks.
Actually where you apply it there is no clearance to copper around the via.
Are you using it this way, because the Saturn PCB toolkit doesn't have provisions otherwise, with vias with no clearance to copper?
(Obviously, a via with copper all around will carry more current, so I guess you cannot go wrong with calculating with clearance)
See screen shot from video.
Thanks.
robertferanec , 09-28-2016, 01:15 PM
I am not 100% sure what you mean, but if you play with the Saturn PCB, you will notice which values can influence the maximum current (not all of them do). The most important is plating thickness - that is the thickness of copper inside the VIA.
It can help to take heat away from the VIA, but to transfer current between layers, the plating is used.
Obviously, a via with copper all around will carry more current
abarnai , 09-28-2016, 06:57 PM
You are right. The ref plane opening diameter doesn't seem to affect it at all. Thanks.
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