Platform forum

OpenRex DDR3 clock termination and Caps connected between 0.75V and 1.5V.

Jupa , 09-01-2016, 11:29 PM
I have attached a picture taken from OpenRexV11.pdf. On the picture I have marked two red circles.

Would like to ask why DDR3 Clock is terminated to 1.5V and not GND?
Also why are you using series termination with Cap and not "traditional" 100R Res between _P and _N signal?
Is it because of better EMI or better signal quality or both?

Another question is, why termination Caps of 0.7V_DDR_VTT are terminated also 1.5V? I have used only termination with GND.

robertferanec , 09-02-2016, 09:54 AM
Hello @Jupa have a look at some other forums, where we discussed VTT decoupling capacitor connections:

- http://www.fedevel.com/designhelp/fo...ecide-vtt-caps
- http://www.fedevel.com/designhelp/fo...memory-routing

Basically, it may depend on what reference planes you are using for your DDR3 signals in your PCB layout.

About the clock: When we were doing the design I was asking the same question as you. I checked couple of other designs and they used the 2xRES+CAP so we did the same. Advantage is, that if there is a problem, you still can unfit the CAP and have "traditional" 100R termination.
MartinHonig , 09-27-2017, 02:04 AM
I have made the same experience just yesterday. I have the signals on adjacent layer with GND and I copied reference design for my MPU (one x16 RAM package only). There is the same 2R+1C to GND circuitry at CLK signals, but it is actually a stub, that continues from RAM BGA to termination passives.

I left the termination non populated and forget about it, because board is working so far. I would like to know more regarding is the termination necessary? For which signals? How does it cope with "on die termination" included in DDR3 chips? In my case it only point to point design, with just one x16 BGA DDR3. The TN4614 from Micron is a good resource but most of these resources is discussing more complex topology than my case.

I tried to use 100R between CLK signals because of the EMI, it helped, but EMI is still too high. EMI is irradiated exactly at DDR frequency (552MHz), when I set RAM to 360MHz, it peak moved exactly to 360MHz (peak is also lower, so I assume board is not able to irradiate this freq so good). Looking hard for a remedy right now
robertferanec , 09-27-2017, 12:04 PM
Martin, maybe it doesn't have to be CLK signal problem. The whole bus is runing at that frequency, so it may be the whole memory bus issue.

What I would try is to check the pin strength settings of memory interface + impedance settings of the memory interface + I would have a look what termination resistors are set in the memory chip and in the memory controller of the CPU. Tweaking the memory controller registers may help you to lower the emissions.
MartinHonig , 10-05-2017, 02:28 AM
I was able to mitigate the emission by a few countermeasures, one of them was not allowing CPU to run at the same clock as RAM.

Unfortunately our MPU vendor is not very open with DDR controller register description, we are currently trying to get support from them to get some answers.
robertferanec , 10-06-2017, 05:28 PM
Please, let me know then if adjusting memory controller registers helped you.
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