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Khai , 08-28-2016, 08:12 PM

Hi Robert and everyone,
How's the ways you used when you layout in Layer 10(project iMX6 Rex)? I can't control length matching when I layout here, please suggest for me the ways I can use to control the length.
Thanks.

robertferanec , 08-30-2016, 05:00 PM

It's combination of several techniques.

1. On the beginning, we draw and do length matching of the last (smallest) segments for two memory chips above each other. Then we copy and place it to the other one.
2. After that, we draw preliminary connections (connect all the ADDR/CMD/CTL pins). Try to place the VIAs which are between the two memory chips into middle between them (so the branches between the memory chips are similar).
3. Then do preliminary length matching of the branches between the memories (that is the most time consuming part).
4. Once it is done, you have more options to length match the longest part of the track. You can use for example xSignals or you can do something what I call "temporarily remove part of layout" (move away from your PCB part of layout - only leave tracks between CPU and ONE memory chip, do the length matching, move the tracks back).

You may watch some of the videos I have done.

• This is a video explainig xSignals (includes T branch): Altium – How to use xSignals ( in Fly-By, T-Branch + Other useful things )
• This is an older video and now you can do track measurement faster (e.g. if you define xSignals, or you use MASK), but maybe it will help you: Altium Designer – DDR2 / DDR3 length matching