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Ethernet PHY part change on i.MX6 Rex - KSZ9031 to KSZ9021 issues

TJose , 10-13-2022, 07:31 AM
Hi team,

Due to parts availability, we have seen the Rex design change from the KSZ9031RNX to older KSZ9021RN part for the ethernet PHY. My company purchases modules (Pro version) as customers of Voipac, and we also have a design that we build in-house which follows it.

Unfortunately, we are having issues with the change from 9031 to the 9021 part on our design. We corrected the ISET resistor (changed from 12.1K to 4.99K) to account for the different requirement on the 9021, however, devices we have built with KSZ9021RN are not able to RX on ethernet. All traffic comes into the device with frame errors.

I wanted to ask if there are any other design changes (or changes to the kernel/dts) that are perhaps necessary to migrate to the 9021 from 9031? Any help is greatly appreciated.


robertferanec , 10-14-2022, 02:50 AM
"we also have a design that we build in-house which follows it."
- you know, that iMX6Rex module license does not allow commercial use of that design, right?

When I was working with these two chips, at that time, one of them had a silicon issue. I would recommend you to consult your issue with the chip manufacturer.
robertferanec , 10-18-2022, 11:11 PM
Thank you @TJose for clarifying the licensing in your email.

About the KSZ chips. It was a long time ago when I was testing them, but I believe one of the differences were skew settings. These depends on layout - I think there are some differences in PCB layout length matching requirements between these two chips. So, you may need to check and possibly adjust settings in RGMII pad skew registers.

From datasheets:
9031: "As the default, after power-up or reset, the KSZ9031RNX RGMII timing conforms to the timing requirements in the RGMII Version 2.0 Specification for internal PHY chip delay.​"
9021: "the KSZ9021RL/RN can be programmed to support RGMII v2.0 with the required data-to-clock skew implemented on-chip. If the delay is not implemented on the PCB and not programmed inside the MAC, the clock skew delay can be implemented via KSZ9021RL/RN registers 260 (104h), 261 (105h) and 262 (106h)."

However, even I setup these registers and the chip appeared to be working properly, one of them had the silicon issue I mentioned above. When we used a freezing spray, the chip stopped working properly (even it supposed to be designed for industrial temperature range). But maybe they fixed it since.
TJose , 10-20-2022, 02:53 PM
Hi again @robertferanec. Thanks for the helpful reply - yes, I'd seen this difference in RGMII versions between the two and have been investigating. I understand how we can configure the registers for timing, though I have not been able to locate in the .dts(i) files this would need to be configured.

My hangup is, with the same software image, the ethernet on the Rex modules we buy work correctly, while ours do not since we had to switch to the 9021 part. No change on the PCB layout. It does not appear to me that 90x1 PHYs have the timing configuration in persistent memory, but... do you by chance recall if this might be the case? Is the skew needed for the 9021 PHY perhaps programmed in production for the Voipac Rex boards? Otherwise yes, maybe we are facing an issue with the silicon on parts we've purchased.

Many thanks and best regards,
robertferanec , 10-21-2022, 01:01 AM
I don't remember exactly, but when I was experimenting with this, I think I set the registers in the driver (where the chip was initialized). Also, I think there was a way to access these registers from command line, so I was able to read them and change them for debugging. Try to search for some kind of RGMII MDIO utility.
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