FEDEVEL
Platform forum

Sreedhar , 12-09-2020, 01:36 AM

Hi Guys,

I have been studying the schematic for imxrex, the ram used in the schematic is MT41J256M16HA-125:E which has a size of 4Gb (256M x 16).

The imxrex have 4 ram bga slots, so if we use the above-mentioned ram, the total ram will amount to (4*4) 16gb? But the total ram size supported by imx6 (MCIMX6Q5EYM10AC) is 4Gb.

Could you please help me in understanding the above doubt.

Regards.
Sreedhar

robertferanec , 12-09-2020, 09:02 AM

Be careful about Gb and GB .. that is what often makes the difference. Also, be careful about bus width e.g. 16bits vs 8bits vs 4bit

So for example:
One way to calculate: 256MB x16 = 512MB x8 => one chip is actually 512MB standard 8 bit bus. If you use four of these chips, that is 2GB in total on iMX6Rex module.
Different way to calculate: If the memory chip is in total 4Gb, then divide it by 8bits to get size in MB: 4Gb = 0.5GB = 512MB

Sreedhar , 12-12-2020, 11:23 PM

Thank you so much, Robert.

Sreedhar , 12-14-2020, 10:45 AM

HI Robert,

I have few more doubts regarding ddr3 for imx6,

1, Is it possible to design the imx6 with only one ddr3 chip (512 MB) ? The imx6 design guide shows 2 Gbyte and 4 Gbyte configurations which has 4 and 8 chips respectively. If we can design with one chip then does it mean the layout is in flyby topology and we need to include termination resistors?

2, I have seen in the reference design guide that imx6 has 32 bit and 64-bit modes. I would like to know if this is configured only in the software or is there a difference in layout other than the number of chips?

3, Is there any difference between layout requirements for ddr3 and ddr3L other than the voltage requirement for imx6 ?

Regards,
Sreedhar

Sreedhar , 12-17-2020, 12:37 AM

Hi,

Can anyone please help me with this?

Regards,
Sreedhar

robertferanec , 12-18-2020, 01:20 AM

1: I don't remember exactly what are all the options. You would need to double check all supported DDR3 bus widths by the CPU. It may only be 64 or 32 bits ... in that case you would need to have 1 DDR3 chip with 32bit bus .... I am not sure if they are available.

If it was possible, you may be able to design it with no termination resistors. But please double check everything I am just writing this from my head.

2. I believe you have to configure this in the registers of memory controller.

Layout: It depends - if you design directly for specific number of chips, then layout is ... classic. If you design to support for both variants, you have to be careful about the unconnected stubs on ADDR/CMD/CT tracks which would go to the unfitted memory chips. Ideally, they would need to be as short as possible.

3. The best is to check reference designs or design guides. Sometimes there may be differences in some recommendations (e.g. termination), but the basic DDR3 connection is the same.