Length equalizing of ADDR_CTRL group from the Lesson 6 of Advanced PCB Layout Course
Rishat , 10-06-2020, 10:14 PM
Hello Robert,
In my activity project «L6-02 - Segment Length Matching - CMD Only» I have fulfilled all the steps for CMD signals:
1) the memory fanouts on the top and on the bottom are length matched within 0,127mm (5 mils)
2) the segments between the memories on the layer 10 are also length matched within 0,127mm (5 mils)
3) then I temporarily removed all tracks from the memory chips 2, 3, 4 on the layers L10, L1 and L12 and length matched rest of the tracks within 0,254mm (10 mils)
4) then I put back all the removed tracks and disabled the length matching rule.
And after that I've seen the whole CMD signals were length matched with tolerance much more then 0,254mm (10 mils). Does it mean that the whole ADDR_CTRL group doesn't have to be length matched within 10 mils? Only the segments length matching matters?
In my activity project «L6-02 - Segment Length Matching - CMD Only» I have fulfilled all the steps for CMD signals:
1) the memory fanouts on the top and on the bottom are length matched within 0,127mm (5 mils)
2) the segments between the memories on the layer 10 are also length matched within 0,127mm (5 mils)
3) then I temporarily removed all tracks from the memory chips 2, 3, 4 on the layers L10, L1 and L12 and length matched rest of the tracks within 0,254mm (10 mils)
4) then I put back all the removed tracks and disabled the length matching rule.
And after that I've seen the whole CMD signals were length matched with tolerance much more then 0,254mm (10 mils). Does it mean that the whole ADDR_CTRL group doesn't have to be length matched within 10 mils? Only the segments length matching matters?
robertferanec , 10-12-2020, 08:31 AM
You still need to be in tolerance if you would create xSignals between CPU and memory chips. This video can help: https://youtu.be/jpk-hfsFaqA
Rishat , 11-04-2020, 09:48 PM
Hello Robert. In this video https://www.youtube.com/watch?v=jpk-...ature=youtu.be you show how to add the DRAM_SDCKE0 xSignal to the ADDR_PP1 (2,3,4) groups. I suppose there should be the same situation with the DRAM_RESET_B signal, shouldn't it? Because the Altium xSignal Wizard doesn't create the DRAM_RESET_B xSignal as well.
robertferanec , 11-06-2020, 05:05 AM
RESET signal is not important. It is an asynchronous signal, means, that signal doesn't need any clock to work (doesn't need to be lenghtmached to clock or other signals)
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