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chitransh92 , 02-06-2020, 12:19 AM

Hello @robertferanec ,
In the open rex design the Caps for the +1V75_DDR_VTT nets are connected in a way that I am unable to understand.

Why the caps are connected with +1V5_DDR net on one side and why not all the caps are connected in Parallel.

Thank you.

Paul van Avesaath , 02-06-2020, 01:02 AM

is there a voltage divider somewhere? this si a very small piece of the schematic..

robertferanec , 02-06-2020, 01:04 AM

They are connected on both sides:
- some are connected between 0.75V and 1.5V
- other are connected between 0.75V and GND

chitransh92 , 02-06-2020, 01:43 AM

@robertferanec .. I understand..
The question why is it done in this fashion???

Are we using the 1.5V rail to provide sufficient transient charge to 0.75 DDR_VTT net??
Or these is some other reason for doing this...

if you can kindly explain..

robertferanec , 02-06-2020, 12:12 PM

Depends on layout and what you use as a reference plane for your ADDR/CMD/CTL signals. If the reference plane is 1.5V, you may want to use capacitors between 0.75V and 1.5V. We use both (GND and 1.5V) as reference planes, so we put there both types of capacitors.

chitransh92 , 02-06-2020, 12:19 PM

@robertferanec , Thank you for the explanation..
I makes some sense to me now...

Are there any more document online where I can increase my understanding on this topic.??
For the DDR3 BGA ICs...

robertferanec , 02-11-2020, 12:33 AM

I have not seen any documents directly saying it like that, but there are some explaing some of the stuff. I think in this Server DDR4 Memory Layout & CPU Power video I used a document speaking about this topic a little bit: https://www.youtube.com/watch?v=rdlEm2xjCsc