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imx6rex-module-in-cadence-master DDR3 Signal Integrity in Cadence

sham , 05-03-2019, 03:07 AM
hi how are you.In Table 25 the

i have simulated board-imx6rex-module-in-cadence-master and got the results in table 2
In table 2 the value of Vix rise is =76.9524mV and
Vix fall is =60.6637mV.
The software show them as error in wave 1 and wave 2 image.
Can you please explain the Vix acceptable value range for ddr3.Also the allowable deviation values
Also tell me how to calculate tdvac,aperture width,tds and tdh.The values given in data sheet donat match the values of simulation.Thanks

robertferanec , 05-03-2019, 09:00 AM
Honestly, I had same questions how to set up the system the way it will pass, but I have been told, most of the time people do not set it up into all the details as it may be very difficult to do (e.g. you may need to consider chip parameters and also memory controller settings). So, what I have been told is, that most people use the simulation to see if the signals are ok or they look bad ... and I often do it same way (if there was something wrong in layout, you would immediately see it even without setting up all the parameters).

But if you play a little bit with the numbers, it is possible to figure out what means what and how to adjust it. I just never had enough time to go too much into details.

PS: When you click into table, it will show you some help (explanation about the parameters) - it is very helpful
sham, 05-03-2019, 10:04 AM
Actually my question is about the difference in the values given in datasheet and the values of simulation.Vix in data sheet is Vix=Vref-150=0.75V-150mV=0.6V Vix=Vref+150=0.75+150mV=0.9V but the simulation value is value of Vix rise is =76.9524mV and Vix fall is =60.6637mV.There is a huge difference.According to data sheet it is not an error but simulation shows it as error.There are also many parameters i will discuss with you.By the way which table are you talking about?I know terms tvac,tds,tdh and also their values are given in data sheet but the problem is the data sheet values and simulation values donot match.i know there may be a difference in pcb layout.
sham , 05-03-2019, 10:49 AM
imx6rex-module-in-cadence-master DDR3 Signal Integrity in Cadence tvac

The value of tvac 70ps in data sheet tvac table image whereas the value of tvac in simulation is 959.355 ps for DRAM D3 signal in my previous post.So you see my question is about the difference in values.not about pcb layout.How does cadence tool measure the values because the way i meaure through data sheet and the way cadence measures there is a huge difference.70ps is the value of tvac but the in cadence the simulated values are greater than 959 ps.So i am confused.
sham, 05-05-2019, 08:06 AM
hi robert can you please refer any document or tutorial that explains the ddr3 simulation parameters that are simulated by cadence.
robertferanec , 05-05-2019, 10:14 AM
hi robert can you please refer any document or tutorial that explains the ddr3 simulation parameters that are simulated by cadence.
- I do not know. When I was making the video, I was doing it directly with Cadence people, so I was not following any documents.

Also, I do not know how to setup the values, but please, when you figure it out, would you share it here? It can help also other people. Thank you.
sham , 07-12-2019, 05:25 AM
hi robert i have a question regarding allegro constraint manager.how can i add nets to bus in.allegro constraint manager for ddr3
robertferanec , 07-15-2019, 02:08 AM
sham , 07-15-2019, 11:15 AM
thanks Robert.In the video it makes the group of all ddr3 signals address,data,control in orcad that leads to data bus in allegro.But whats the procedure for separate group pf address,data and control lines for ddr3 in orcad that leads to separate address bus,data bus and control bus .As afterwords for pin delay i have to insert the .csv file .The pin delay requires bus of data and address/control.Thanks
robertferanec , 07-17-2019, 06:09 AM
I do not use Bus in Allegro. But maybe this can help you https://www.youtube.com/watch?v=lp9yzrQzVhI
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