FEDEVEL
Platform forum

ChinoPR , 09-23-2024, 03:16 PM

Hi everyone, sorry for the rather basic question!! I'm doing a project with DDR3 for the first time (Phil Salmony Course), my question is the following:

Layer 3 (for high speed) all the signals from the same data bank I make coincide in ps, then in another high speed Layer as well... but what happens for example at the top? Where a DDR pin is in the middle of the BGA and another from the same data bank is on the periphery and routed, I can't make the delays "match" in that case since several of those pins are quickly routed to a via from inside the BGA. I'm attaching an image where I have the DDRs (in blue) where I have some on the periphery and others inside the chip area. When that happens, what should I prioritize? That the delays match Layer to Layer, or that the total sum of the delays of the signals match? Any advice or documentation to read?
Thank you very much.

Robert Feranec , 09-25-2024, 07:42 AM

if you are doing length matching based on ps, you don't need to follow same/similar length on every layer (if the tool calculates delay correctly, but I have no idea how good is altium in this and if it considers different speed outside and inside of layers). Also even if you are doing it based on track length, for DDR3 having different lengths on top layer should not be a problem. I don't know your DDR3 speed, but usually it is not so "fast"

ChinoPR , 09-26-2024, 06:17 PM

Robert, it's you, I can't believe it. Thank you for your reply and thank you for all the help you give us. I'm an electronic engineer and you've inspired me a lot. Regards from Argentina!!