FEDEVEL
Platform forum

Induranga Randika , 12-16-2024, 05:42 PM

The attached image is from the design of Advanced Digital Hardware design course by Fedevel.

I know the relevant power good signal is open-drain and that was the reason to use A pull up. And also he mentioned the R104 & C105 make a low pass filter to delay the Power good signal.

But shouldn't we connect the resistor in series with the PG signal to make a low pass filter or RC delay rather than making it parallel ? Here it is in parallel with the capacitor.

Am I missed something?

Induranga Randika , 12-16-2024, 07:00 PM

@Phil

Phil , 12-16-2024, 07:37 PM

R103 and C105 form the low-pass filter/delay. The R104 is a placeholder to ensure the PG signal is low at start-up (which should be the case 'within' the PG pin of the regulator).

QDrives , 12-16-2024, 07:54 PM

You only want a slow (delayed) turn on, turn off should be (near) instantaneously.

Induranga Randika , 12-16-2024, 10:04 PM

Thanks @Phil and @QDrives Got it now.

Induranga Randika , 12-16-2024, 11:48 PM

Another question @Phil . Do we have any specific delay constraints to match ? I mean, any specifc reason for going for 12K with a 100nF . It has typically 2.6mS approximately.

Is that delayed signal is for some extra safety to ensure that it will not turn on approxiamtely same time ? The reaosn I am asking is these times are very small. Their should definitely have a minimum time gap to identify each turning on, as discrete power on stages.

Any specific delay gaps ?

Induranga Randika , 12-16-2024, 11:49 PM

may be 12K and 100nF, coz of bom consolidation too. But interesting to know that we should follow any minimum gap ?