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Induranga Randika , 12-13-2024, 08:48 PM

Hello Guys,

I have a question regarding the Phil's 07th lesson. In the attached screenshot, you can see he used an open drain buffer with a pull up for Power On Reset function of Zynq 7000 series SoC. The requirement of that signal is that, it need to be pulled low during the power on sequence and need to pull back to high after power sequencing done. So I can clearly understand that we can use the power good signal for this as it changed as the requirement.

My problem is why can't we omit the open drain buffer and just use the pull up only ? Even though if we omit the buffer, the power good signal will be Low until the power sequence done, and will come to high after its done. So why a simple pull up can't do it ? In most MCU's or ICs, if the RST is active low, what we normally do is just pulling up the line and adding a switch to a ground. In this case why they specifically use an buffer ?

They could have just omit it and connect the PG_3V3 line directly to that pullup ? Please help me Phil.

#zettbrett #𝐐＆𝐀-forum @Phil

QDrives , 12-13-2024, 09:53 PM

The most important question is: what is the voltage of the power good signal?
The SN74LVC1G probably has a higher voltage tolerance than the Zynq.
The second question is what is the rise time of the power good signal? It may be to slow the Zynq.

Robert Feranec , 12-14-2024, 11:33 AM

also, is PG_3V3 only connected in one place?

Induranga Randika , 12-14-2024, 12:41 PM

Thank you for your responses. @QDrives The PG signal is 3V3. The POR signal is also 3V3 since its in the voltage domain of the bank0(According to user guide UG933) of the PS of the Zynq SoC . (Bank0 is powered from 3V3)

Induranga Randika , 12-14-2024, 12:43 PM

Thank you @Robert Feranec . Its connected to a mezzanine connector also. May be to use with an external signal from a carrier board or any other switch

Induranga Randika , 12-14-2024, 06:00 PM

Any help ?

QDrives , 12-14-2024, 08:20 PM

Do you have a screenshot of the power supply part that shows the power good signal there?

Induranga Randika , 12-14-2024, 10:11 PM

yes

Induranga Randika , 12-14-2024, 10:11 PM

check the below close-up image too

QDrives , 12-14-2024, 10:14 PM

So the power good signal is **not** 3.3V!

Induranga Randika , 12-14-2024, 10:19 PM

that means, the purpose is just level shifting ?

QDrives , 12-14-2024, 10:22 PM

In a sense yes.
Personally I would do the pull-up for the power good from the 3.3V itself.

QDrives , 12-14-2024, 10:27 PM

Then again, the LED also uses the power good signal. If you use the same signal for reset, the LED would turn off when you externally reset the SoC.

Induranga Randika , 12-14-2024, 10:31 PM

Oh yes. I got it now. Also, if we just pull the NPOR low by using a switch or something when the system is running (That means when PG is high), may be that PG signal can be shorted to ground even though the PG should remain high. Now I can understand it. He has just isolated the signal not to have any effect from the NPOR signal

Induranga Randika , 12-14-2024, 10:34 PM

Thank you so much for the help