FEDEVEL
Platform forum

Mike Rowlands , 01-04-2017, 08:15 AM

Hi,

I am looking at the tasks for the week and am a little confused as to what is needed to be done.
This is in the context of the video advising to do "fan out" of complete BGA (and other devices) first, and not to rush into connecting interfaces together.

"EASY: Fanout the Ethernet PHY interface using micro VIAs on the CPU side
(Connect the RXD series resistors and make the fanout the way to avoid stubs.)

ADVANCED: Do fanout for Ethernet PHY & HDMI Interface
(Think about how to avoid signal crossing, use only minimum signal layers.
Connect the RXD series resistors and make the fanout the way to avoid stubs.
Fanout HDMI interface using micro and buried VIAs, use layer L10 for the layout.)

EXPERT: Fanout all the interfaces under the CPU
(Plan how you will do the layout. Start with the difficult interfaces with a lot of signals and high frequency.
Use the same topology for all the signals in one interface. Be sure all the pins of the CPU have fanout.)"

How much tracking is involved?

- "Fan-out" is normally a connection from pad to vias, presenting a connection point (via) on the main routing layer.

- Elsewhere, I read of the term "BGA escape", which is routing a track to outside of the BGA border.

- "Layout" or "Connect" of tracking is routing and connecting tracks between the two (or more) vias (or pins) that need to be connected.

The EASY exercise appears to be asking for complete pin-to-pin connection of the uP IC to the PHY IC, not just the fan-out of the 2 ICs.
The ADVANCED exercise also seems also to ask for complete connection.
The EXPERT exercise seems to be asking for all the interfaces to be completed, but all the unimportant connections just to have fan-out (connection to a via available for routing).

Please can you advise whether each task is asking for Fanout to a via, Escape to the edge of the device, or complete connections to be made.

Thanks.

robertferanec , 01-04-2017, 06:55 PM

Hi @Mike Rowlands, you can just do CPU fanout or as you mentioned "BGA escape". Basically route the CPU pins out from the CPU BGA footprint. You do not need to route the complete nets (for the PHY, you may want to connect CPU with series termination resistors). If you have any other questions, just let me know.