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jpartis1 , 07-20-2018, 07:36 AM

It's been some time since I created a PCB using Altium and I just created my stackup, and double clicked on each ground plane to assign the net as GND.

> I don't remember if that was all there was to it?

Isn't it true that Altium considers any polygon pour on a plane to mean that you want to remove copper in that area.

> Am I correct?

Finally, regarding ground planes:

> Should I connect them all together, and allow the signal to find it's way to the ground plane, or should I force the signal to go to the closest ground play by using a uVia?
> Also, since I am trying to minimize stubs, should I be using thru-hole vias for returns, since they will have a stub?

Thanks!!

robertferanec , 07-24-2018, 02:38 AM

- Double click on a plane to assign Net - that is correct
- Planes are negative layers. That means, anything drawn on Plane layer is with NO copper
- I use through hole VIAs for Powers and Grounds (all ground planes are stitched together)
- I have never seen anything mentioned about STUBs on ground VIAs. Anyone has some info about this?

jpartis1 , 07-25-2018, 07:21 AM

Hi Robert, thanks for that confirmation!
I think I was getting confused with pouring copper planes on top and bottom layer.
I remember having to "shelve" polygons and got confused about the planes.

Regarding the STUBs on ground VIAs, I was thinking about a rule I found a long time ago which I've incorporated into my layout process that considers ever path (trace, via, etc) as both a DC and AC signal. That way, it considers any noise which may be present on the power. So my thoughts are that even if you have a DC power plane, and you connect to it through a VIA, if there is high frequency noise on that power, it must have a return path parallel to the power, so I always place extra ground VIAs close to the power, that way the noise signal will be able to follow the power trace/VIA, etc back home by jumping to the proper ground plane closest to the power plane. Even though DC power is not considered 'high frequency', any noise riding on that DC would be.

Do you agree with that assumption?

robertferanec , 07-26-2018, 11:39 PM

I have seen and read some design guides describing optimum placement of power VIAs (including power VIAs around decoupling capacitors), so you may try to google for these (I do not remember which documents I exactly read). Personally, when I am designing boards, there is usually not many options - often I need to place VIAs were some free space is. However, there really are optimum ways for VIA placement and I also try to think about return currents when placing for example decoupling capacitors and power / GND VIAs.

This may not answer your question, but I am not really expert for this, so maybe the best will be if you search for some documents on Internet.