Platform forum

Vias under IC microcontroller

Eoliveira , 02-27-2018, 10:46 AM
Hello Robert !!

Is it correct to place vias under IC to connect nets ?
For example my board has a microcontroller, case TQFP 32, there are a lot of pins and my PCB has 2 layers.


noisepic , 02-27-2018, 04:35 PM
I'm not Robert but i can give some ideas: find the answer for these question.

- does your IC have expose pad? If NO there's no problem.
- is it easy for you to debug?
robertferanec , 02-28-2018, 09:12 PM
@Eoliveira, could you add some screenshots?

@noisepic thank you Excellent points!
Eoliveira , 03-01-2018, 05:12 PM
Hello Robert.
How are you?
I hope you're fine

1. This board has two female headers to connect external circuits (2x14), and two female headers (1x8) to connect external modules from MikroElektronika. ( MicroBus ) ...
We are proud to announce that we have made 100 Click boards™ in partnership with Microchip. One hundred unique...

I placed two vias under MCU ... I don't know if it's a good practise

2. Do you have any suggestion to following situation?

I want to measure current value ( I ) from MCU to test Low power modes, I placed a header (1 x 2 ) and put together all points (VDD pin from MCU) in pin 2 and pin 1 I connected to source .
I was looking for the best way to do this.in Altium. and Net Tie look a good option.
Is net tie the best way to do.?
There are rules to setup ?

Thank you very much for your assistance !!!
robertferanec , 03-04-2018, 08:42 AM
1) If the MCU is the chip in the middle, you should be fine with VIAs under the chip (I think I see the two VIAs you are referring to).
2) I often use BEADs or 0R on power rails. In case I need to measure the currents, I just remove these components and use DVM to measure the current. The BEADs will also help to filter power. Net ties are also good.

What you may want to consider are current loops. I would try to keep GND on the bottom as solid as possible (e.g. in current layout you are splitting the bottom layer with the orange power track. I would probably route as much as possible on the top and I would use bottom layer only for GND and if needed, I would route short tracks of other signals on the bottom in the places where I would need to cross other signals ... possibly I would use bottom layer for some horizontal routing, but I would be careful to keep the GND as big as possible)
Eoliveira , 05-03-2018, 06:24 PM
Hello !!
This is my board after to finish !!! It is an PIC24F Curiosity CLONE .
What Can I do to Improve ? Gimme your opinion !!

robertferanec , 05-06-2018, 06:05 PM
@Eoliveira, do you have any specific questions?
Eoliveira , 05-08-2018, 08:06 AM

1) About the Angle of position from Microcontroler on the middle
of board. Are there issues or restrictions to use
this type of position.

2) I placed polygon on TOP LAYER: +3v3 (yellow) and +5V(orange)
Is there any problem about distance between regulator and
circuit that Will be supplied ? e.g MicroBus, where I Will connect
others boards.

robertferanec , 05-08-2018, 05:18 PM
1) I have seen many boards with components placed by 45Deg. If you are using reflow soldering, I think that should be fine. If you are using wave soldering - then I do not know (I do not use wave soldering). But this is just my opinion. Just to be sure, you may want to double check it with your Assembly house.

2) If I have to use something like this, I would maybe place also some bigger caps (e.g. 10uF) between power and GND close to the block of components/connectors which are going to need power from that power rail (especially far end of this track). I would also use some smaller caps (e.g. 100nF) close to the power pins. The caps may help to filter the power and keep voltage level same even if there are some peaks in currents (+ that may help also whit EMC/EMI).

Basically, very simple to say, when you place a bigger cap at the far end of the power track (far away from power supply), this capacitor will be working as a small local power supply. So if there is a quick pulse which requires bigger current, the circuit doesn't have to take the power from the power supply, it will take it from the local capacitor which is much closer. Capacitor will then slowly be charged back from the power supply. That is much better situation, than travelling this bigger pulse through hole long power track. However, that is a very simple explanation
dbvanhorn , 06-25-2018, 10:20 AM
In my current design I have placed an array of vias 9 x 9 under the processor (81 vias!) The board is six layers, Ground polygons on all layers, one layer under the processor is solid ground, and one is VCC. Extensive stitching vias all over the board. Some call me paranoid about noise but low noise is critical to this design, and I usually get through radiated emissions testing without them being able to tell if my system is on or off, despite the processor and switching power supply. Power to the MCU comes up to the top level through vias, then runs through X2Y bypass caps to the processor. Johanson 100x14x105MV4T or similar.

As long as the chip does not have a soldered pad, I don't see any issue with putting vias under the processor. MAYBE there could be a problem if what you did resulted in the processor not sitting flat on the board, like routing a track under the processor on one side and having bare dielectric under the other side. I tent all my vias under parts or not, except where I intend the via to also be a test point.
Use our interactive Discord forum to reply or ask new questions.
Discord invite
Discord forum link (after invitation)

Didn't find what you were looking for?