FEDEVEL
Platform forum

noisepic , 07-21-2017, 09:17 AM

Hi Fedevel,

I'm new to high speed design, I'm designing DDR3 interface with lacking of tool. What I have is datasheet and follow rule of matching length. Big my concern is that: I don't have package length of SoC and DDR3 information. Also don't have $ to purchase professional software to simulate SI like: SiWave, Hyperlynx..Tool is 100Mhz oscillo BW, I believe I'm in front of failure.

How could I overcome over my situation. So far I think about the interposer for the first version and make some adjustment for timing.
Do you have any advise?
Thanks

robertferanec , 07-22-2017, 12:00 AM

- If the length in package is important, the chip manufacturer would usually said the information in datasheet / design guide. Otherwise you may assume that they length match the signals

- If you are not sure, the safest way in your case may be copy and paste memory layout from the reference design (that is the same way how I started).

noisepic , 07-22-2017, 06:53 AM

unfortunately I dont have layout reference design of SoC. Chip supplier doesnt support, that the way I try to look for a way. Any suggestion?