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oscargomezf , 09-23-2016, 04:46 AM

Hi everyone,

I'm starting with the impedance calculations. I made everything with Saturn PCB design. And this is my result PCB stack up and track geometry - 8 layer.png I think the calculations are ok, but obviously I'm not completely sure. These are me calculations for DIFF90, DIFF100 and DIFF50.

L1 (Ref L2), L8 (Ref L7):

Class Name Width(um) Space(um) DIFF Theoretical Value SE Theoretical Value Target Value
DIFF90 203 213 89,9840 49,9670 90 / 50
DIFF100 192 370 100,0030 51,6130 100 / 50
SE50 245 - - 50,0003 50

L3 (Ref L2/L4), L6(Ref L5/L7):

Class Name Width(um) Space(um) DIFF Theoretical Value SE Theoretical Value Target Value
DIFF90 146 184 89,9930 50,0050 90 / 50
DIFF100 146 650 99,6540 50,0050 100 / 50
SE50 146 - - 50,0050 50

The manufacturer where I'm going to manufacture the PCB (VI CLASS) has a minimum width/space track (external layer) for 35um of 15mm and a minimum width/space track (internal layer) for 35um of 12.5mm. --> This paragraph is worng.

The manufacturer where I'm going to manufacture the PCB (VI CLASS) has a minimum width/space track (external layer) of 0.15mm (for 35um Cu) and a minimum width/space track (internal layer) of 0.125mm (for 35um).

What do you think about my geometry?
Do you think it can be right?

Best regards.

robertferanec , 09-26-2016, 08:47 AM

Hi @oscargomezf, I had a look and here are my comments:

- 35um minim width / space ... wow. Who is that PCB manufacturer (if we may know)?
- if possible, we do not specify material and material thickness as we are never sure what they have (unless we already have a PCB stackup from that manufacturer and we just need to adjust it)
- what I noticed, many manufacturers don't place 35um into inner layers (I do not know why), so do not be surprised if they want to change it.
- L3 will be closer to L4 (so L4 will influence it more). We normally use L2 as GND, so we very often place L3 closer to L2 as L4 is many times power (and especially for PCBs below 10 layers, the L4 is usually a power plane with power islands, so not a solid plane, however, I am not sure how it is in your case).
- I checked DIFF90 on L1 and our calculations look similar. Normally we round the values (e.g. instead of 203um we would just use 200)

Go ahead, try to check with your PCB manufacturer and see what they will send you back.

oscargomezf , 09-26-2016, 09:49 AM

Hi Robert,

According to: "35um minim width / space ... wow. Who is that PCB manufacturer (if we may know)?"

I'm sorry. I made a mistake. I made the corrections in the ticket: "The manufacturer where I'm going to manufacture the PCB (VI CLASS) has a minimum width/space track (external layer) of 0.15mm (for 35um Cu) and a minimum width/space track (internal layer) of 0.125mm (for 35um)."

And If I use V-Class has a minimum width/space track (external layer) of 0.15mm (for 35um Cu) and a minimum width/space track (internal layer) of 0.15mm (for 35um)."

According to: "If possible, we do not specify material and material thickness as we are never sure what they have (unless we already have a PCB stack up from that manufacturer and we just need to adjust it)" and "what I noticed, many manufacturers don't place 35um into inner layers (I do not know why), so do not be surprised if they want to change it."

The stack-up is from the manufacturer Lab Circuits from Spain with the code BU-730: http://lab-circuits.com/uploads/doc/...LabCode730.pdf

According to: "L3 will be closer to L4 (so L4 will influence it more). We normally use L2 as GND, so we very often place L3 closer to L2 as L4 is many times power (and especially for PCBs below 10 layers, the L4 is usually a power plane with power islands, so not a solid plane, however, I am not sure how it is in your case)."

I think I've got another error in the image stack-up, the correct use of the 8-layer stack-up is: L1 - L2(GND) - L3 - L4 (Power) - L5(GND) - L6 - L7(Power) - L8

And yes in the power plane I'm planning to use power islands, but where the differential signal are going to be trace I'll have to try to avoid this.

But as you said, the structure [L2(GND)- (130um)- L3 - (240um) -L4(POWER)] is asymmetrical, so Do you think is better to use a symmetrical structure?

Probably the best option for my it uses this BU-301 of 10 layers: http://lab-circuits.com/uploads/doc/...LabCode301.pdf

I'm going to try to do the calculations again analysing the results for BU-301.
I'll show you the results if you see something odd about the dimensions I get.


Thank you very much, Robert.

robertferanec , 09-26-2016, 01:00 PM

The space doesn't have to be symmetrical, I just prefer to have full GND plane closer to signal layer, as the closer layer influence the track properties more. So, theoretically you can just swap the dielectricum thickness, however then you may not be able to get the proper core / prepreg materials.

oscargomezf , 09-27-2016, 01:25 AM

Sorry, but I didn't understand you well.

My idea is to use a standard stack up from the manufacturer, so I prefer don't change the stack-up because I don't know If it will be able to manufacture.

Then If I choose to use the BU-730 with 8 Layer. Is this structure right?

L1(Signal) - L2(GND Plane) - L3(Signal) - L4(PWR plane) - L5(GND Plane) - L6(Signal) - L7(PWR Plane) - L8(Signal)

I've got two different types of structure where I'm going to develop my impedance calculations:

L1 (with L2 reference [GND Plane])
L8 (with L7 reference [PWR Plane])

And

L3 (with L2 reference [GND Plane] & L4 reference [PWR Plane])
L6 (with L5 reference [GND Plane] & L7 reference [PWR Plane])

I understand that I can use the L2(GND) & L4(PWR) like reference in the microstrip and stripline structure, that is to say, Can I use PWR planes like a reference in the impedance calculations of microstrip and stripline structures?

Obviously, in the Power planes, the differential lines have to be placed in continuous power planes, and I'll have to avoid route lines between planes.


I attached you two screenshots of my differential imedance calculations:

i) L1_L8_microstrip_DIFF100_Saturn_PCB_Design.png
ii) L3_L6_stripline_DIFF100_Saturn_PCB_Design.png

robertferanec , 09-27-2016, 07:58 AM

The thing is, the BU-730 has distance between L2-L3 = 240um and distance between L3-L4 = 130um. If your POWER plane (L4) is going to be solid and if your POWER plane is a good reference plane, then this is ok.

However, I always prefer GND (L2) to be the closer reference plane (this is my personal preference as GND is usually a good reference plane). Closer reference plane influences the signal layer much more comparing the further reference plane (again, this is my own opinion) - that is why I prefer GND plane to be closer to signal layer. In BU-730, this is not possible.

This all is based on my own opinion. If you use it as you are suggesting, it probably will work fine - I may be just too picky

oscargomezf , 09-27-2016, 08:39 AM

Thank you for your prompt reply.

I understand what you mean.

I'm too picky too, so I'm going to change my strategy. I'm thinking about using a 10-layer with this structure:

L1 - Signal
L2 - GND Plane
L3 - Signal
L4 - GND Plane
L5 - Power Plane
L6 - Power Plane
L7 - GND Plane
L8 - Signal
L9 - GND Plane
L10 - Signal

I'm working on a project which there are a lot of expensive components, so the price of the PCB is not critical. It doesn't matter 5 euros more.

I read that this stack up is very good from the point of view of EMI. I'm going to have the same effective layers for signals, but now I've got two more GND planes and I don't have to concern about the power planes because they are between two GND planes.

​
What do you think about this stack-up?

I attached a screenshot of PCB stack up and track geometry suggestion. I had to change the internal copper thickness, it was very difficult to get consistent values, so I realised that change this value from 35um to 18um, I got consistent values since a value of W=0.146 mm and S = 0.65 mm for DIFF100 it's too big.


Thank you very much.

robertferanec , 09-27-2016, 08:44 AM

Yes, I like this one. I use it a lot.
PS: For power planes, you may want to use thicker copper.

robertferanec , 10-16-2016, 09:14 AM

yes, higher currents, lower impedance, better heat conductor, ...