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DDR3 memory routing
ljo , 06-15-2016, 05:23 AM
Hello,
I was looking at the beaglebone black project and I have a question about ddr3 memory routing.
If I understand the High Speed signals rules in lesson 4 (advanced pcb layout course), each signal group has to be routed same way. But in beaglebone black project, for example the data signal group is not routed the same way, I mean it uses different layers(top, L3 and bottom). For example, DDR_D2 is routed on top layer and DDR_D0 on layer 3(see screenshot). The board works apparently(i dont have it at home). my question is how the board can work this way?
here is the screenshot of the board on which i just highlighted the data signal group:
I was looking at the beaglebone black project and I have a question about ddr3 memory routing.
If I understand the High Speed signals rules in lesson 4 (advanced pcb layout course), each signal group has to be routed same way. But in beaglebone black project, for example the data signal group is not routed the same way, I mean it uses different layers(top, L3 and bottom). For example, DDR_D2 is routed on top layer and DDR_D0 on layer 3(see screenshot). The board works apparently(i dont have it at home). my question is how the board can work this way?
here is the screenshot of the board on which i just highlighted the data signal group:
mairomaster , 06-15-2016, 06:02 AM
It is normally a compromise when you don't have the space to do it on a single layer (Top + 1 internal layer). The problem in this case is that the signals travel with a different speed on the different layers and you should take this into account if you want to achieve tight timing tolerances. Then it is not enough anymore to make all signals the same length - the faster signals will need to be shorter to compensate. This complicates the length matching quite a bit. A part of the story is that there is no very easy way to accurately know the speed of the signals on the particular layers. Calculators - like Saturn PCB can give you an approximation of that.
The engineers who designed Beaglebone are good enough to know about that and consider if it will be a problem. If you don't consider it, you might be lucky and everything could be fine because it happened that you fit in the tolerances, but you might not be that lucky in other cases...
The engineers who designed Beaglebone are good enough to know about that and consider if it will be a problem. If you don't consider it, you might be lucky and everything could be fine because it happened that you fit in the tolerances, but you might not be that lucky in other cases...
Comments:
ljo, 06-15-2016, 09:53 AM
Thank you @mairomaster.Ok in this case for my project i will do my best to route signals same way.
robertferanec , 06-15-2016, 12:09 PM
Yep, you can do that, but I never do it. Once we outsourced memory layout and the guy was lazy and did not followed this rule. When we run memory tests in environmental chamber, some boards were failing at -20C.
They probably tested beaglebone and it is probably just fine.
But be careful. I know, that many engineers do not extensively test their boards and many developers think it is normal when a board occasionally freezes / crashes / reset. Especially young engineers think, that once a board is running on your table in your lab for 1 hour, that everything is done perfectly and everything is working. After time they usually find out, that may not really be true and some problems only can be found when the boards are running under high stress conditions.
They probably tested beaglebone and it is probably just fine.
But be careful. I know, that many engineers do not extensively test their boards and many developers think it is normal when a board occasionally freezes / crashes / reset. Especially young engineers think, that once a board is running on your table in your lab for 1 hour, that everything is done perfectly and everything is working. After time they usually find out, that may not really be true and some problems only can be found when the boards are running under high stress conditions.
ljo , 06-15-2016, 05:22 PM
Ok thank you robertferanec.
I have also an other question:
In the micron design guide they said:
"Systems using FBGA-packaged DDR components typically split PCB planes between VDD and VSS such that DQ, DQS, DM, and clock signals maintain a VSS reference, while address, command, and control signals maintain a VDD reference"
For me it means that i can use for the adress control command class the vdd plane as a reference instead of gnd plane, am i right? Is there any pb if i dont use a gnd plane for reference?
I have also an other question:
In the micron design guide they said:
"Systems using FBGA-packaged DDR components typically split PCB planes between VDD and VSS such that DQ, DQS, DM, and clock signals maintain a VSS reference, while address, command, and control signals maintain a VDD reference"
For me it means that i can use for the adress control command class the vdd plane as a reference instead of gnd plane, am i right? Is there any pb if i dont use a gnd plane for reference?
mairomaster , 06-16-2016, 01:34 AM
That sounds interesting, can you provide a link to the design guide?
My guess would be that this is valid for a low layer count boards (4-6 layers) where you might not have enough ground planes. Using power plane as a reference is a bit tricky and I am trying to avoid it when I can.
Robert can give a better opinion on this, he as good experience with DIMM modules and other related stuff.
My guess would be that this is valid for a low layer count boards (4-6 layers) where you might not have enough ground planes. Using power plane as a reference is a bit tricky and I am trying to avoid it when I can.
Robert can give a better opinion on this, he as good experience with DIMM modules and other related stuff.
ljo , 06-16-2016, 03:21 AM
here is the link:
robertferanec , 06-16-2016, 03:35 AM
Yes, @mairomaster is right. I have seen using this technique mostly on 6 layer PCBs. For example, there is many decoupling capacitors between VDD-VSS which are short circuits for high speed signals. Also, you may want to place VTT decoupling capacitors between VTT-VSS and VTT-VDD.
One guy told me once, that for DDR3 ADD/CTL/CMD signals, the VDD reference plane may be even better as GND, but this is not confirmed.
If possible, I try to avoid using power planes as reference planes. Usually, the plane which is closer to the signal layer, I use as a solid GND plane and this is my good reference plane. The plane which is further from the signal layer, I try to have as GND, if not possible, it may also be a Power plane.
One guy told me once, that for DDR3 ADD/CTL/CMD signals, the VDD reference plane may be even better as GND, but this is not confirmed.
If possible, I try to avoid using power planes as reference planes. Usually, the plane which is closer to the signal layer, I use as a solid GND plane and this is my good reference plane. The plane which is further from the signal layer, I try to have as GND, if not possible, it may also be a Power plane.
ljo , 06-16-2016, 09:27 AM
I have just read this in the am3358 ti soc datasheet. It was written in minuscule 
:
"Additional bypass capacitors are required when using the VDDS_DDR plane as the reference plane to allow the return current to jump between the VDDS_DDR plane and the ground plane when the net class switches layers at a via"
So you are right. I know that i can do it but if i can avoid i will do otherwise.
Thank you!
:"Additional bypass capacitors are required when using the VDDS_DDR plane as the reference plane to allow the return current to jump between the VDDS_DDR plane and the ground plane when the net class switches layers at a via"
So you are right. I know that i can do it but if i can avoid i will do otherwise.
Thank you!
koreshx , 06-21-2016, 10:24 AM
I had similar question and found answer here, thanks!
What about symmetrical board? If board has symmetrical structure we have corresponding layer for each layer with exactly the same signal speed (?). If we use this pair of symmetrical layers may be we shouldn't worry about track length on each of layers?
Or is it misconception?
Originally posted by mairomaster
Or is it misconception?
mairomaster , 06-21-2016, 10:51 AM
Yes, if you are using two symmetrical layers, you shouldn't worry.
robertferanec , 06-23-2016, 07:42 AM
What about symmetrical board? If board has symmetrical structure we have corresponding layer for each layer with exactly the same signal speed (?). If we use this pair of symmetrical layers may be we shouldn't worry about track length on each of layers?
Or is it misconception?
Or is it misconception?
ljo , 07-13-2016, 03:02 AM
hello,
For information related to the question I asked in the beginning of this topic:
I asked in the ti forum the following question:
"I have a question about routing ddr3 signals on different layers. I saw that in bbb in a same group for example dq0 the signals are routed on different layers. I dont understand how it works since the signals travel in different speed betwen outer layers and inner layerS. Can someone explain me?"
this is the answer from one guy from ti:
"The difference in speed propagation can be ignored at these trace lengths and frequencies."
For information the maximum DDR CLK speed in am3358 is 400MHZ. There is only one ddr chip and it is placed very close to the processor(max trace length less than 900 mils).
What do you think?
For information related to the question I asked in the beginning of this topic:
I asked in the ti forum the following question:
"I have a question about routing ddr3 signals on different layers. I saw that in bbb in a same group for example dq0 the signals are routed on different layers. I dont understand how it works since the signals travel in different speed betwen outer layers and inner layerS. Can someone explain me?"
this is the answer from one guy from ti:
"The difference in speed propagation can be ignored at these trace lengths and frequencies."
For information the maximum DDR CLK speed in am3358 is 400MHZ. There is only one ddr chip and it is placed very close to the processor(max trace length less than 900 mils).
What do you think?
robertferanec , 07-13-2016, 11:47 AM
The clock of the board which I mentioned before (the one not routed properly and failing memory test at -20C) was 533MHz.
About the TI comment, I think nothing. I am pretty sure there are situation where you can ignore some stuff, but I do not see any reason why I should be ignoring it when I know how it should be done properly.
When someone look at your work, they should see, that you really like what you do and you try to do it right. And I rather length match the board, than risking of spending hundreds of hours with debugging randomly failing board .... and in the worst case re-designing the board completely.
About the TI comment, I think nothing. I am pretty sure there are situation where you can ignore some stuff, but I do not see any reason why I should be ignoring it when I know how it should be done properly.
When someone look at your work, they should see, that you really like what you do and you try to do it right. And I rather length match the board, than risking of spending hundreds of hours with debugging randomly failing board .... and in the worst case re-designing the board completely.
Akteevy , 09-25-2017, 02:49 PM
"Routing groups the same way", "keeping the same number vias", etc. are simplifications.
The real goal in high speed routing is to bring the signal in time and in shape. If you are so lucky as to have at hand good SI tools like Hyperlynx, then you can do whatever you like, as long as your signal meet the delay budget and pass the eye diagram and other requirements.
Even the "length match" rule is misleading and we, engineers, should not be mistaken by simplifications... We match delays, not physical length. Here comes why the advice of "same layers, same number of vias, etc." - this way we ensure the delay would be proportional to the length. But even this is wrong: For the same total length, a straight trace will have less impedance (and less delay) than other with accordions.
The real goal in high speed routing is to bring the signal in time and in shape. If you are so lucky as to have at hand good SI tools like Hyperlynx, then you can do whatever you like, as long as your signal meet the delay budget and pass the eye diagram and other requirements.
Even the "length match" rule is misleading and we, engineers, should not be mistaken by simplifications... We match delays, not physical length. Here comes why the advice of "same layers, same number of vias, etc." - this way we ensure the delay would be proportional to the length. But even this is wrong: For the same total length, a straight trace will have less impedance (and less delay) than other with accordions.
robertferanec , 09-25-2017, 05:09 PM
"Routing groups the same way", "keeping the same number vias", etc. are simplifications.
If you are so lucky as to have at hand good SI tools like Hyperlynx, then you can do whatever you like, as long as your signal meet the delay budget and pass the eye diagram and other requirements.
Very often happen, that your PCB is not manufactured by same PCB manufacturer over the whole life of the board. Very often different PCB manufacturer has to adjust PCB stackup. If PCB is length matched based on delay, any changes in PCB stackup may influence individual signal delay and what can happen, you change PCB manufacturer and your PCB suddenly stops working reliably.
I had a case, when a board which was 100% passing simulations, had memory issues and memory was not working reliably. This was the layout done based on delay (I mentioned that board in the previous discussion). However, I have never had a failing board which was length matched based on "group routed the same way".
Of course, even when you are doing length matching based on "groups being routed the same way", you should keep in mind, that the main goal of doing this, is because of signal delay, not because you would like to have all signals the same length. Everybody should definitely understand what is behind length matching.
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