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BGA FANOUT
ljo , 05-28-2016, 11:23 AM
I have a question about CPU fanout. I am a beginner in the PCB layout. I have a project which is simple (one SOC AM3358 TI + one UART interface + 1 DDR3 memory chip + one PMIC TPS65217C). That s all. I want to begin with the minimum. So now im doing the SOC fanout. In the attachement i sent you a screenshoot of the SOC BGA with GND pins highlighted. Can I connect multiple pads to a single via because otherwise it is really painful? I mean Will the SOC work if it is done this way?
mairomaster , 05-29-2016, 03:59 AM
It is not optimal but in some cases you need to do it. The key is to try to minimize it as much as possible, since it can eventually create problems which are hard to troubleshoot.
Why do you think you can't use separate vias? What is limiting the space you have? In your cases, since you barely have any interfaces wired, you are probably doing something wrong if you need to share too many vias. Give us some more information please.
It could be very useful to you if you can check some reference designs with this SoC or find a design guide for it or for a similar one.
Why do you think you can't use separate vias? What is limiting the space you have? In your cases, since you barely have any interfaces wired, you are probably doing something wrong if you need to share too many vias. Give us some more information please.
It could be very useful to you if you can check some reference designs with this SoC or find a design guide for it or for a similar one.
robertferanec , 05-29-2016, 09:28 AM
I absolutely agree with @mairomaster. I guess, you will need to adjust placement. Have a look at the reference design or have a look at other boards like
OpenRex.
Yep, doing layout is sometimes hard. If it was simple (only connecting points), everybody would be doing it 
OpenRex.
otherwise it is really painful
ljo , 05-30-2016, 03:34 PM
Thank you mairomaster and robertferanec. I will adjust placement. I need training ☺. It s my first pcb.
ljo , 05-31-2016, 12:04 PM
I have another question about BGA FANOUT:
If a decoupling cap have not access to a GND pin on the processor, can i create a VIA(through hole top bottom) which will be connected to GND layer as the screenshot?
If a decoupling cap have not access to a GND pin on the processor, can i create a VIA(through hole top bottom) which will be connected to GND layer as the screenshot?
robertferanec , 06-01-2016, 12:25 AM
Yes, you can.
BTW: Just yesterday I had a webinar exactly about this topic: Advanced PCB Layout - CPU, Memory & BGA Power Fanout (Free)
BTW: Just yesterday I had a webinar exactly about this topic: Advanced PCB Layout - CPU, Memory & BGA Power Fanout (Free)
ljo , 06-01-2016, 08:59 AM
Ok great thank you robertferanec.
ljo , 06-04-2016, 12:02 PM
For example if i have 5 power pins in my bga and i have to connect 2 decoupling cap to these pins, do i have to connect these caps to all pins or can i just connect two pins to these 2 caps and connect the others pins to the power plane?
Comments:
robertferanec, 06-06-2016, 12:50 AM
Usually we use 1 cap per pin (or as recommended by design guide). If the pins are located in one area all together, you can share the caps the way as you described, but if they are located in opposite corners of the BGA, I would definitely use 1 cap per pin.
ljo , 06-05-2016, 09:58 AM
hi,
i was looking at the imx6 rex layout and i see in the bga fanout that all the power/GND pins share vias. As said in this topic, it is not optimum, but it is donet. What is the reason? is it a space issue?
i was looking at the imx6 rex layout and i see in the bga fanout that all the power/GND pins share vias. As said in this topic, it is not optimum, but it is donet. What is the reason? is it a space issue?
robertferanec , 06-06-2016, 12:47 AM
Have a look at the bottom - there are decoupling capacitors and it was not possible to use one power VIA per one power pin.
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