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Questions from Learn Altium Essentials Second Edition

Jetstream4 , 07-26-2023, 08:45 AM
Hi everyone,

My first post here. I have recently completed Learn Altium Essentials Second Edition course and I have the following questions. I have tried re-watching the videos multiple times but I missed the explanation for the following. I would appreciate if someone can clarify these questions.

1. Logic behind using ground planes - How many should be used and where they should be used.

2. Why are certain signals routed in Layer 3 in the course - Is there any requirement/good practice? How would I know which signals should be routed in layer 3 (i.e. not on top/bottom layers). Did Robert carefully choose not to route the signals he routed in layer 3 in the beginning of the layout, so that he can route them in layer 3 later or did he randomly route the signals until that point and then decided to route the remaining signals in layer 3

3. How does a layer get attached to a net - If no vias are placed in the PCB? (In the course we assign GND net to layer 2 and layer 5 before any VIAs are placed in the PCB. Does this connection happen through the pads we already have on the PWA. How will this connection happen if we don't have any pads or vias on the PCB?)


qdrives , 07-26-2023, 01:37 PM
robertferanec , 08-03-2023, 01:52 AM
1. In ideal world, you may want to have GND planes above and below each signal layer. Also in ideal world you may want to have GND plane close under components (the second layer and before the last layers). Also you may want to have GND planes as neighbor layers around power planes.

The question is not how many, but why we need them. Solid GND planes help fields do not spread all over the board or escaping board. I recommend to watch some of my videos about how signal travels and how power is delivered. It will help you to understand what GND planes do in PCB.

Of course, we don't live in ideal world and you will need to make compromises e.g. often you may be able only use one solid GND plane - in this case place it close to the signal layer.

2. It's related to my answer at point 1. We placed the noisy signals inside of the PCB so we can control how the fields will travel. This means, we make the board less noisy

3. you connect the layers via through hole pads and vias.
katepalmes , 08-14-2023, 02:58 AM
Ground planes are crucial for providing a solid reference point for your signals and helping manage electromagnetic interference. Typically, you'd want to have at least one solid ground plane (like a bottom layer) and possibly a power plane (like a top layer) if you're using a multilayer board. The ground planes should be strategically placed to ensure good return paths for your signals and reduce noise. It's often recommended to have a continuous ground plane on the layer adjacent to your signal layers. Navigating the realm of business communication can be a complex dance, and that's where business writing services like no other come into play. These services are more than wordsmiths; they're architects of impactful communication. As a business professional striving for clarity and influence, I've found these services to be a compass guiding me through intricate strategies and persuasive pitches. Their knack for transforming ideas into polished narratives is a testament to their expertise. Here's to the business writing services that elevate our communication game and empower us to thrive in the competitive world of commerce.
gyuunyuu1989 , 08-26-2023, 08:11 PM
The capacitor that goes onto the LDO pin was chosen to be a "Low ESL" feature capacitor but the ones before it. Why is that so?

The capacitor that goes to the SMPS output pin is specified (in datasheet example) as having ESR of 4mohm. Isn't this just the minimum value ESR and one can use this or larger value. Or does one need to use this specific value?

The ISL6236EVAL2 BOM lists some manufacturers as "GENERIC". What does this really mean?

During creation of the 200k resistor, there are features that contain terms "AEC-Q200" "High Voltage" "Moisture Resistant". What do these really mean?

The datasheet example schematic for ISL6236A only gives the part number for a single component on the page itself. This is the transistor SI4816BDY. Why did they mention the part number itself while this was not done for the inductor?
gyuunyuu1989 , 08-27-2023, 10:50 AM
I have finished lesson 1 of the Learn Altium Essentials Second Edition​. The lesson 2 is still locked. Why is this so?
robertferanec, 08-30-2023, 01:26 AM
Maybe you signed up for Online version? You can double check if you send an email to info@fedevel.com then Marcela or Dominik will check your account and help you.
qdrives , 08-27-2023, 02:55 PM
The ESR of the capacitor highly depends on the regulator. There are some regulators that cannot have a low ESR, there are some that require a low ESR.
If the ESR on the output capacitor is low, it can more easily supply transient currents.

Often, it does not matter which manufacturer make the resistor, capacitor or inductor as the differences between them are not important for the design.
Take a 4.7k pull-up resistor - if it has a tolerance of 10% it is no problem.
If it is used for a precision measurement and needs to be 0.1%, does it matter who makes it? Probably not.

AEC-Q200 is an automotive quality system. One could argue that they are a bit more reliable.
High voltage - guessing here as I never needed one (that I know of), but consider how resistors are made. This could be a film that is laser trimmed. "High voltage" could mean that that trimming would not cause a problem with higher voltages.
Moisture resistance - again a guess that the resistor is less hygroscopic, which could alter the resistance.

For FETs there are a lot of parameters that can influence the result. Naturally, that is also true for other parts, but in this case the FETs are driven by the controller. For most other components the specifications are not so strict, or, in the case of the inductor, are less of a concern to Renesas. However, do not forget "politics" here.
gyuunyuu1989 , 08-27-2023, 03:31 PM
Thanks qdrives.

When the resistor says high voltage, the confusion is that high voltage means high current. This means high power dissipation. But SMT resistors are only rated for very low power. So what significance does "high voltage" have? Does high voltage mean millions of volts or hundreds of volts?

Is there ever any need to use other than 100 mil grid during the schematic creation? During schematic symbol creation, Robert used all grid sizes during creation of the symbol graphics using the line tool.

For IC schematic symbol, should vertical spacing between pins be 100 mil or 200 mil? Robert created the SMPS IC to have 200 mil spaced pins in the schematic symbol.

From the course it seems that the schematic symbol comment field is set during component creation and then it never changes in the schematic. Is this correct or there are exceptions?

Sometimes we show things other than component value in the comment field e.g MLCC voltage rating, inductor DC resistance, resistor power rating. At other times the comment field will only mention the component value and nothing else. Why is this so?

What does "soft termination" mean for MLCC?

Finally; Robert did not go into why we are using certain type of resistor or capacitor. I am referring to the material. We are using mostly ceramic capacitors and then some tantalum I believe. The resistors I believe are thick film resistors. On digikey I come across these options under composition: Carbon Composition, Carbon Film Ceramic, Metal Element, Metal Film, Metal Foil, Thick Film, Thin Film Wirewound​. How does one know which material resistor to use?
qdrives , 08-28-2023, 02:56 PM
High voltage resistors

Lets do a search on Digikey for high voltage resistors... So all that are high voltage in the feature, lets limit to 0603 types.
The first 3 resistors in the list were 25M, 100M and 50M ohm. That is Mega ohm. With 100V and the 100M the resistor only dissipates 10mW. So power wise, no problem.
Now the 4th on the list is a 1k resistor. There 100V would give you a power issue (10W!)

I can tell you that the 350V limiting element voltage is twice what most other resistors have.
Now you may ask "But if the voltage cannot be across it because of the power limit?" True, for 1k power would be the limit. However, this family resistors can also be 10M. So, 100mW, the rated power. Now do a short time overload, that is only possible with a higher voltage.

If we look at the datasheet of the first in the list, we see the resistive element of the resistor.
Notice the zig-zag pattern? If a spark would jump, how much would it 'cross' the resistor? If this pattern would be 90 rotated, it would almost completely skip the resistive element.

High voltage is also to prevent sparks from crossing the resistor. It should go through it, not across it.

For drawing the schematic in general there is no need to have anything other than 100mil grid. Especially for placing symbols, you want them on 100mil grid.
When designing the symbol, there are reasons, like adding the 'curls' for schottky or zener diodes. Or details in FETs, bipolar transistors, etc.
Pins should always be on the 100mil grid.

As you may have noticed I did not make it hard on the schematic. However, for esthetic reasons I have some text (like designator) on a 50mil grid in the symbol.
Altium has a bug that if you move that text, even an undo does not restore it to the original position, but on the grid.
At such times I set the grid to 50mil to restore the text to the correct position.

100mil vs 200mil
There are times when it is convenient if the pins are 200mil or more apart. 100mil is for MCU, CPU, etc., but for (SMPS) regulators or other drivers, 200mils may create a more clean schematic.
Take the next bit of schematic.

Here the pins are either 200mil or even 400mil apart. This reduces the number of direction changes the lines in the schematic need to make.
Take a look at pin 2 and 3 going to R1003 and R1005.
If the schematic would be more clean and you have the space, go for 200mil.

Symbol comment change in schematic
In part that is a personal preference. I too set the comment when I create the symbol and do not change it in the schematic.
There are 2 parameters that I change in the schematic (2 that I can think of):
1) Label - used for connectors to state what is connected to it (ie. power in, motor, programming, etc.) These are created in the library with a "?" and changed on the schematic.
2) Remarks - For special remarks like gluing the component after assembly or a resistor that needs to be mounted off board (raised) due to the heat it produces.
But I do not have any exception on the comment field.

Symbol comment change in schematic
Again that is a personal preference. I still vary a bit with the comment field. Mostly because I have no real use for it.
But for resistors I have i.e. "Res 0402 10E"

Soft termination
When a board flexes, stresses are exerted on the components. With capacitors they have a tendency to create a short when it goes bad in if flexed to far.
With soft termination that the capacitor should be beter able to withstand such stresses, or at least, not cause a short.

Thick film resistors are the cheapest. Wire wound have more inductance (often problematic) but higher power(?) and metal film are often more accurate. And we (or should I say others) could go on with all the pro's and con's of the various resistor elements.

For capacitors there is the ESR, ESL, safety, DC and AC bias, aging, humidity, temperature stability, accuracy next to capacity, voltage rating, price and availability.
I use 3 types of capacitors:
- Hybrid Aluminum - Polymer Capacitors -- for the bulk capacitance.
- X7R/X7S -- for the medium high capacity (HAS DC+AC bias, aging ~3%/decade hour and temperature offset ~15%)
- NP0 -- for timing, low capacitance or where I do not want DC bias effect.
gyuunyuu1989 , 08-28-2023, 03:00 PM
thanks qdrives,

With this topic of reflow soldering and wave soldering that has been mentioned in lesson 3. I can see that both are done by machines in factory setting. One thing I am confused about is, are both applicable to SMT and Through Hole components or wavesoldering is only used with through hole and reflow is only used with SMT? Also, is there a tendancy to apply some sort of glue under components when PCB goes into machine upside down so the components do not fall off due to gravity?
qdrives , 08-28-2023, 03:07 PM
Better start a new thread in the future.

Wave soldering can be applied for both SMD and through hole components. However, there are limitations to SMD like pin pitch and orientation. So resistor, capacitors and SOT23 are no problem.
From experience, do not try a SC88 package with lead free -- you get about 10% shorts.

For through hole there is also the PiP or THR, Pin-in-Paste and Through Hole Reflow are techniques that solder TH using paste in the reflow over. This is mainly used for connectors so that there is a single soldering action (thermal stress).

If you do SMD and wave soldering the components need to be glued.
When doing two sided reflow, it often is not necessary.
In all my cases the assembly contractor wants to control the gluing of the components (or not).
gyuunyuu1989 , 08-29-2023, 12:42 PM
Thanks qdrives.

I have reached lesson 3 already.

I have found that while Robert is creating a unique schematic symbol for each specific part, it is possible to assign multiple footprints to a single schematic symbol in Altium. Robert has not used thie feature though. A single part number from manufacturer defines a specific component which also includes its package. What does it mean when Altium designer makes it possible for a user to add multiple PCB footprints for the same component? It does not make sense at all.

The Altium PCB Footprint Wizard contains a list for which it guides the user through a step-by-step process culminating in a PCB footprint. This wizard shows options (among others) for capacitor, resistor and diode. All three of these are two terminal components with almost the same type of footprint (only silkscreen might differ to show polarization). What is the point of having different options for capacitor, resistor and diode footprints and then not even mention inductor? This is also a strange observation.

Robert created the PCB footprint for the ISL6236A IC. He changed the solder mask expansion to 2mil. I can see that this makes the gaps between the solder mask cut-out larger and this will make it easier to manufacture the board. But, where did he get the 2mil value from? Some datasheeet or IPC standard or just personel preference?
qdrives , 08-29-2023, 03:41 PM
I have assign multiple footprint to a symbol in past. One was for reflow soldering and another for wave soldering.
Components need bigger pads when wave soldering then for reflow.
Naturally it is possible to use the large wave solder pads also for reflow, but then the component can be soldered at an angle and it just does not look nice.

I create different footprints for resistors and capacitors too.
1) The height of the components are different. The height is a footprint parameter and may change the size of the pads.
2) I use a different 3D model
3) Even use a different color for C0G compared to X7R capacitors as in reality this is often the case too.

0402 resistor, 0603 X7R cap, 0402 res, 0603 res, 0402 C0G cap, 0402 X7R cap, 0805 cap.

You PCB fabricator should be able to tell you what the limits are.
Take this one: https://www.eurocircuits.com/pcb-des...es/soldermask/
For green LDI soldermask, the minimum expansion can be as low as 0.03mm
However, some fabricators (perhaps even most), kind of ignore the soldermask expansion you provide and just set their own.
The only time I can think of when this would be a problem is when you have SMD (here Solder Mask Defined) pads. They have a negative expansion.
Also, normally you do not set the soldermask expansion in the footprint, but let the board design rules dictate it. That way you can easily change for a different fabricator or technology.
gyuunyuu1989 , 08-30-2023, 02:57 AM
I had missed the fact that height is also an important factor for the pad size.

Robert used a single document which listed the footprint details for different packages of resistors and capacitors. The size list was split into two parts, wave soldering pad dimensions and reflow soldering pad dimensions.

This document did not take into consideration the height of the component. It just said for 0805 package use this pad size and for 1206 package use this other pad size. Won't the same package size (e.g 1206, 0805 e.t.c) chip resistors and capacitors, have the same height?
gyuunyuu1989 , 09-02-2023, 01:44 PM
I have progressed to the part where Robert created the last footprint required for PCB creation, in the lesson 3.

Robert did not create and use any "testpoints" although this would be considered highly important. Why is this so?

Robert did not create any mounting holes. The holes that have been created are solely to make connections I believe. Why is this so?

Although Robert marked components with large NF in red, I believe there is a built in method in Altium to specify what PCB variant to create. Robert did not teach this in the lesson series so far. Is this topic covered?

For the tantalum capacitor T530X337M010ATE004, the document T2076_T52X-530 contains footprint information for Density Levels A, B and C. Woudn't any designer just go for the smallest footprint (level C) since a Level C footprint could be used in all cases but a level A footprint cannot be used in levels B and C?
qdrives , 09-02-2023, 04:27 PM
Won't the same package size (e.g 1206, 0805 e.t.c) chip resistors and capacitors, have the same height?
No, yes and no
No, the not all res/cap in the same footprint has the same height, but
Yes, if you allow for some tolerance, most of them will be equal enough (i.e. 0.4...0.65mm for resistors)
However, for the bigger size capacitors (0805 and larger) there are low capacitance caps (relative to their size) that are significant lower than those pushing the capabilities. So no.

Robert did not create and use any "testpoints" although this would be considered highly important. Why is this so?​
Testpoint are only used when you want to do automated testing using a bed of nails (or flying probe).
I have designed many boards and almost all of them were only tested at the (TH) connectors. So the bed of nails connected to the connector pins.
As designer you do not (need to) change the position of connectors as much as your traces. Each time you do, you may also need to change the bed of nails if a testpoint had moved too.

Robert did not create any mounting holes. The holes that have been created are solely to make connections I believe. Why is this so?
There are other mounting methods then mounting holes, mostly, this would require a dedicated housing.
However, mounting holes is often better regarding tolerances.

Although Robert marked components with large NF in red, I believe there is a built in method in Altium to specify what PCB variant to create. Robert did not teach this in the lesson series so far. Is this topic covered?
I do not know how old the video is, but older versions of Altium did not support variants.
And even if you have a component in a variant, especially not fitted, it is best to also show this in the normal schematic.

For the tantalum capacitor T530X337M010ATE004, the document T2076_T52X-530 contains footprint information for Density Levels A, B and C. Woudn't any designer just go for the smallest footprint (level C) since a Level C footprint could be used in all cases but a level A footprint cannot be used in levels B and C?
There are 3 density levels: least, nominal and most.
Explained here: https://youtu.be/cMxXea16Hxc?t=1502
gyuunyuu1989 , 09-05-2023, 02:19 PM
I am about mid-way in the lesson 4. Robert created a stackup which looks like this:

How come FR4 (the di-electric) is in the bottom? The dielectric is supposed to be in the middle right? Aren't stack-ups supposed to be symmetrical with the di-electric in the center and the prepreg and signal/plane copper on either side in pairs e.g copper, prepreg, copper, prepreg, dielectric (FR-4), prepreg, copper, prepreg, copper.

The other thing that robert mentioned at around 54:15 "... on signal layer you draw the tracks. On the plane you basically draw the spaces between the objects. I don't want to confuse you but if you are not sure, always just use signal layers ... on signal layers you draw the tracks. On plane layer if you draw something, it will be space"

This raises a few questions.
1. What does it mean to draw space between the objects?
2. If we can always just use signal layers so as not to be confused, why do plane layers even exist in the first place?
qdrives , 09-05-2023, 06:04 PM
It is a strange stack-up for sure. However, I have not done the lessons so cannot comment correctly on it. Perhaps @robertferanec can explain if he has time to spare during his trip to China.

Anyhow, 'normal' stack-ups are (for 6 layers):
Top - prepreg - Int1 - core - Int2 - prepreg - Int3 - core - Int4 - prepreg - Bottom.
So the dielectric changes from core to prepreg. This is the cheapest production form. 2x core with copper (etch inner layers), single press, drill, plating and etch outer layer.
So far I have not yet seen any video explain PCB production is sufficient detail that makes it all clear.

Using multiple prepregs on the outside is common for multistage microvias, but this requires multiple press cycles and will increase the cost a lot (together with plating as they take a long time)

As for planes I cannot tell you much as I do not use planes, only polygon pours. As far as I know, you cannot draw on planes, only do split planes (space between?)

As for 2 -- good question. perhaps it makes the layout a bit simpler. And another thing is some elements of Altium (signal integrity?) can only work with planes.
I do not think that planes need "repouring" so that would be at least one advantage.
gyuunyuu1989 , 09-06-2023, 03:31 AM
ok, I am confused between prepreg and core. The core is the actual mass of FR4 that makes most of the the PCB volume and provides it mechanical strength. The prepreg is a thin layer of dielectric to separate the different copper layers. So there should be just one core because we start with a core and then add layers onto it as required.
gyuunyuu1989 , 09-06-2023, 11:19 AM
After Robert set the layers to plane in the layer stackup manager, going to that layer in the PCB view shows copper. I thought we had to carry out a copper pour manually to get copper in that layer but already has copper. How is that possible?

If we are careful we should still be allowed to place maybe a few tracks on the ground or power plane players right, as long as we know that it will not cause signal integrity issues elsewhere. Am I correct in this assumption?
qdrives , 09-07-2023, 03:35 PM
Both core and prepreg are the same material -- FR4 in simple terms.
The difference between them is that the core is fully cured and hard while the prepreg is not.
Here is a bit an explanation on the build-up https://www.youtube.com/watch?v=67WhV0EDqCA

A plane has copper as standard and you 'remove' it with i.e. via's and through hole pads. You are not allowed to place traces on plane layers (not possible with Altium).
If you want to do so, you should make it a signal layer, place a polygon and the rest is up to you.
gyuunyuu1989 , 09-23-2023, 05:37 PM
ok, now I am going through the lesson 4. I can see that for each of the signals PHASE1 and PHASE2, Robert has created a polygon pour on the top layer to link the FET transistor IC with the inductor. He then used tracks to link the SMPS controller IC to this polygon pour.

The this is, the signal track on the inner layer is 1mm. The signal track on the bottom layer is 0.5mm. The SMPS IC is on the bottom layer and one tiny segment of the track that is otherwise 0.5mm is actually left at its older length of 0.2mm. This 0.2mm segment connects to the SMPS controller IC pad. I have attached image of this for clarification.

If the track has to be made thicker for reason of current carrying capability, shoudn't the entire track be 0.5mm or 1mm?

Also, since the IC pad itself is so small, is there really a need to use track thicker than the IC pad?

By keeping one segment at 0.2mm right next to the IC pad, it seems that this small piece will become a lot hotter than the rest of the track.

While we are using 1mm thick track on the PCB, what did the designer's do inside the IC package with bonding wires? Are they and the silicon really capable of handling large currents?

I just find this strange and inconsistent.


Another question that arises is that since some nets require special attention. Is there a specific reason that Robert did not create net classes in the schematic for them?
qdrives , 09-24-2023, 01:55 PM
Often on boards of Robert, the inner layers are 18um copper (0.5oz) while the outer layers are 35um (1oz). This is due to plating. This also means that outer layer traces can be about 1/2 the width of inner layer traces with the same current carrying ability.

​One of the reasons to use 0.2mm trace width to connect to the IC is that the pad of the IC could be 0.2mm and using a wider trace would 'protrude' the trace across the pad and reduce the clearance to the next pad. However, the wide trace could be started closer to the pad so that it would not show a narrow.

That short section that is narrow would not get much hotter than the rest of the trace as it would cool down to that other parts. Is is like a heat sink on the trace.

For the bond wire it also depends on the material and thermal resistance of that material, but the manufacturer will have tested it.

Why would he need net classes? I use them often to indicate the voltage of those nets, but that is for 24V and 60V. If all you do i work < 10V, there is a lot less need for netclasses.
gyuunyuu1989 , 09-24-2023, 03:09 PM
Since some nets need to be thicker, I had assumed that net class could help define specific constraints for thickness and this way if we forget to follow the correct guidelines, then the Altium DRC will flag up error.
qdrives , 09-25-2023, 03:23 PM
No, that is a common mistake many people make.
Let's consider a motor controller that needs to drive 25A. You need wide traces to get the current from the input to the output.
Now you also want to measure the voltage of that. Does the sense trace need to wide as well?

Trace width is (often) just a point to point thing, especially when going in the more (extreme) high currents.
gyuunyuu1989 , 09-29-2023, 02:43 PM
Rober said that some tracks need to be made thicker since they will carry lot of current. In some places Robert created copper pour in place of track in lesson 5. OK fair enough.

Rober set some things to 1mm and other things to 0.5mm. However, I don't think he gave any justification for this specific figure anywhere. What could be the reason for choosing 0.5mm rather than 0.4mm or some other value? Why not use 0.55mm?

In the lesson 6, Robert creates an outline of the PCB. For this, he ceates a new Mechanical layer. When the mechanical layer is created, the layer type is left as "N/A". Looking at what type of Mechanical layers can be created, the list is "Assembly Notes", "Board", "Dimensions", "Fab Notes", "V Cut", "Route Tool Path", "Sheet" and "Board Shape". The question that arises is that, why did Robert leave the Type as N/A? Certainly one of the existing types means board shape or outline doesn't it? Why not select that?

I am reaching the end of the lesson 6. To generate the output files for the project i.e assembly and Gerber, Robert used the .OutFile that can be created for a project. Here, Robert generated the assembly file and gerber files.

From what I know, the assembly file is supposed to show the outline of each component with its designator inside the outline. However, the assembly file that Robert created contains only the copper information for top and bottom layers. Why is this so? Also, Robert did not create assembly layer inside the PCB footprints that would be used in generation of the assembly file.

Now the thing is,
1. We can generate the assembly drawing (Altium 22.2) from File -> Assembly Outputs -> Assembly Drawing
2. We can generate the geber files (Altium 22.2) from File -> Fabrication Outputs -> Gerber Files (Or Gerber X2 Files)

So why didn't Robert used this method to generate the assembly drawing and the gerber files?
qdrives , 10-01-2023, 01:18 PM
Wider traces
So why 0.5mm... Both Robert and I are metric persons. That makes use prefer 1mm, 0.5mm, 0.25mm and smaller to the limits of the fabricator/copper thickness.
I sometimes do 0.6mm if I want as wide as possible and one of the components can only handle 0.6mm traces without getting clearance violations.
There are 2 simple rules for selecting wider traces:
1) It is a power line and 0.5mm or 1mm is wide enough for the losses (both voltage and thermal) and there is space for them.
2) High current traces - use PCB toolkit or something like it to find out what the temperature rise would be with the current. If possible keep it below 10°C temperature rise.

Board outline
Robert started using Altium before or at version 10. I started with 10 to evaluate and my first design was in 12.
In those versions, there was no "board outline" mechanical layer, nor any of the other (3D, courtyard, assembly, etc.) Just overlay, solder mask, paste mask.
At that time, you had a table (ie Excel) where you had layer 15 as the courtyard, layer 13 as top 3D, etc.
Today it is nice that you can assign layer types. When importing data from other sources that has thing on different layers, Altium will place it on your corresponding layers.
With the old versions, you had to do this manually.
Now I cannot actually speak for Robert, but I still occasionally forget to assign the layer type.

Exporting data
On exporting data, Robert could have made a long video or multiple training lessons alone.
There are so many things that can be said about it and it can bring everything done together.
In the old days I had a single JobFile that did all the exports. Now I have 3 - for fabrication, for assembly, and for 'documentation'.
The first 2 (fabrication and assembly) will be transferred (i.e. emailed) to external parties. The last (documentation) is for internal use only.
By having 3 JobFiles, you can use the project releaser to streamline the release process - configure once, export many times.
Generating the exports from File -> .... is the most 'manual' way, time consuming (for multiple projects / exports) and error prone.
See attached project on what I export and the JobFile to get that.
gyuunyuu1989 , 10-01-2023, 03:03 PM
Thanks. I saw a different course from Robert that is free on youtube and covers the basics of Altium. At that time, Robert created an assembly layer inside the footprints, the top assembly layer is purple in colour. He also put a string that would contain the component designator into the middle of the assembly layer symbol.

The assembly drawing that was created in that course showed outline of components and outlines of the board. It did not show any copper areas. In the assembly drawing we could see where R1, R120, C33 e.t.c go and what area they occupy. Now in this course, Robert created an assembly drawing that shows black for where the copper goes on the top and bottom layers. I am quite confused.
qdrives , 10-02-2023, 02:10 PM
There are 3 simple questions you should ask. The answer may a little more complicated.
1) What do YOU want in the drawing?
2) What do others (like your ASSEMBLY COMPANY) want in the drawing?
3) Do you need a drawing at all?
In other words: WHO needs WHAT?

In my opinion the answer for 3 is "yes" and the answer for 1 and 2 - see the previous attached project.
However, do note that there is no perfect answer, nor is there a perfect assembly drawing / documentation.
gyuunyuu1989 , 10-02-2023, 03:24 PM
I am learning PCB design subject so I can use it in the future. From what I have scene so far, I have come across two type of drawings.

The first type is where it just shows a lot of boxes with designators in the center of each box. Each box represents the area occupied by a component at a specific location. I have used such a document to find where components on a schematic exist.

The second type I have come across is rather wierd. It shows the copper for different layers of the board. It has several pages. One or more pages will have a list of notes that are numbered. I have never been able to fully understand these but I have scene other people giving a lot of importance to these documents.

Both of these are called assembly drawing.

What Robert created was something that can be used to print the circuit copper area to a copper board which will then be dipped into acid. This transfer from paper to copper can be done using an iron I believe. The acid will dissolve the areas where black toner does not exist. Several hours later, we shall take out the board and wash it. Then we will drill holes for through hole pads or vias. We migh need to put in some pins and solder them for the via hole to connect top and bottom side. Anyway, that is a different topic.

Robert did create the first type of assembly drawing on his FREE Introduction to Altium Designer course on youtube. So I was confused why he did not do that here again.

Anyway, I am basically at end of the course. I would recommend that Robert should introduce the viewers to a program called Saturn PCB Toolkit. It is a free program from Saturn PCB Design Inc.

Although there are a few things that I believe should have been covered in this course or atleast touched upon, I still think this course is worth every cent and highly recommended.

Thanks qdrives and Robert.
qdrives , 10-03-2023, 02:24 PM
To start with the last: https://www.youtube.com/watch?v=fJCRrEf_IH8

For an assembly drawing -- take a look at page 3 of the attached document.

Your description of type 2 documentation seems to be more a fabrication drawing. That has a different purpose -> producing the bare board.
The assembly drawing is for the components on the board.
Both of these documents can be found in the project I attached earlier.
gyuunyuu1989 , 10-10-2023, 11:51 AM
In the course Robert created many PCB footprints. In a few cases he said that the footprint dimensions available from documentation are not suitable for hand soldering and we should use different dimensions for the pads. Robert never gave any justification for the numbers he used. Also, why hand solder when we can use solder paste through laser cut stencil followed by heat gun?
qdrives , 10-10-2023, 02:02 PM
why hand solder when we can use solder paste through laser cut stencil followed by heat gun?
Because that is a bit difficult for rework/repair.

Robert never gave any justification for the numbers he used
If Robert is like me, he is 'guessing' that the adjusted dimensions will be good.
Do note that it can never be "good" as it is either good for automatic production or good for manual soldering. There can be a compromise between acceptable for both.
This is part experience.
gyuunyuu1989 , 10-10-2023, 04:35 PM
A machine will just pick and place components and then use an oven to solder the stuff. So if the pads are larger to make hand soldering easy, why is that a problem?
qdrives , 10-11-2023, 01:17 PM
With large pads the part can drift.
I used to use large pads for manual soldering. Now with the smaller pads everything looks a lot better (straight).
In more extreme cases the drifting parts can cause shorts with parts next to it if both drift towards each other.
gyuunyuu1989 , 10-11-2023, 07:57 PM
I see, I did not know that. So parts can drift when they are being soldered because the solder spreads on copper and the copper area is quite large.

By the way, sometimes I see someone have a large copper area connecting some points together (like the voltage rails on SMPS controller). Then, they suddenly use thermal relief. The thermal relief will reduce how much current can travel. So it seems counter intuitive to have large copper polygon and then use thermal relief for component pads.
qdrives , 10-12-2023, 12:51 PM
So parts can drift when they are being soldered because the solder spreads on copper and the copper area is quite large.
Correct. See the picture here https://blog.thedigisource.com/3-common-pcba-defects where is states "component shift"

Thermal relief
So do you have the large polygon for the current or for thermally cooling the part?
If it is just the current, the thermal relief will cause some heat generation it that point, but it will be cooled by the larger copper just next to it. So for current it is not that much of an issue.

However, if you want the polygon also to act as a heatsink to the component -- that does not work.

In most cases it wil be just for the current.
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