Platform forum

Routing DDR3/4 in Altium designer to FPGA BGA package

gyuunyuu1989 , 05-24-2023, 07:43 AM
Robert Feranec has a multitude of videos on youtube that cover the topic of routing of the high speed signals. I am talking specifically about DDR3/4 but this applies to anything that needs impedance control and length matching. However, the videos I have found so far, are covering only one aspect or part of the process.

Does Robert have, on youtube or on the paid courses, a step-by-step guide that cover the entire process of creating the schematic connections for the DDR3/4 RAM and then use net classes and/or xsignals, assign the relevant design rules and then finally do the complete layout in the PCB editor. Does such a video exist?
Paul van Avesaath , 05-25-2023, 03:24 AM
look i am not saying you are not looking but literally searching for xsignal in youtube... second hit

This video explains how to setup xSignals and do length matching in Fly-by & T-Branch DDR3 memory layout. It also shows how to setup xSignals with passive co...
gyuunyuu1989 , 05-25-2023, 04:59 AM
Will watching these two videos cover the entire topic to sufficient detail?
Paul van Avesaath , 05-25-2023, 05:16 AM
did you watch it ?
gyuunyuu1989 , 05-26-2023, 08:30 PM
I shall watch the 45min video tomorrow, I have seen 2 videos on this topic yet. Now there is a small confusion here. The objective in high speed PCB design is matchin the propagation delay of different PCB tracks closely. This would be done by using length matching but the thing is that usually a signal would move across different layers as it goes from source to destination and the propagation delay on each layer shall not be the same. This means that although the total length of a signal may be equal, the way its different sections are spread across different layers, shall give a different amount of total propagation delay. This brings us to the main question, why does Altium designer focus on length matching rather than propagation delay matching, or did I miss something?
robertferanec , 05-27-2023, 01:32 AM
it should be matched by time, however:
- time delay numbers may not be very accurate in some softwares
- if you match by time, it can be hard to do some changes e.g. if you need to change PCB manufacturer and you will need to change stackup (heights of layers), that could make problems

so there are techniques which make the process easier and still good enough. For example:
- you route all the signals in the group the same way - all the signals what need to be lenghtmatch together go through the same layers in the same order
- and for each signal in the group you may route similar length on the top and bottom layers vs length inside of PCB
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