FEDEVEL
Platform forum

everdrone , 07-31-2025, 04:43 PM

Managed to route everything on 6 layers as pictured. What do you think? Could there be a more space-efficient or better arrangement?

Robert Feranec , 08-02-2025, 09:16 AM

does the bga have all the other pins unconnected?

everdrone , 08-02-2025, 09:35 AM

No, the trace and debug pins are acid green, SAI are dark green, I2c1 and I2c2 are bright pink

everdrone , 08-02-2025, 09:36 AM

all the power supply pins have either an 0201 capacitor already placed underneath or they are connected to a larger capacitor on the top layer

everdrone , 08-02-2025, 09:36 AM

I will just need a few more pins from the edge of the BGA to addressa multiplexer

everdrone , 08-02-2025, 09:37 AM

ah also the ADC pins are dark blue (top right corner)

everdrone , 08-02-2025, 09:39 AM

do you think I should have placed the sdram chip on another side? to avoid all the traces running under the chip?

Robert Feranec , 08-02-2025, 09:52 AM

My advice is, before you start connecting anything to BGA, fan out all the BGA pins - means all powers, all signals, place all vias, connect all decoupling caps under BGA ... go with all the signals you will need to connect out of the BGA edge (for example 2mm away from BGA). Only after that start routing the signals outside of the BGA. If not done this way, often you will route 95% of all the BGA pins and then you will find out there is no other way to continue and you will have to re-route a lot of work. You can try to continue, but it looks like many signals are routed under the BGA - this can make layout hard and I dont normally route signals under bga unless there really is no other way.

everdrone , 08-02-2025, 09:55 AM

Thanks for the advice, I will save this version and try routing most of it away from under the chip area