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BGA Decoupling Paths seem long in this Example
miner_tom , 12-14-2018, 08:12 PM
Hi Robert, I am going though your Advanced Layout Course now and I really love it! Although at Altium I am a novice I have spent many years supervising layouts and have spent more time than I care to remember in EMI labs finding the source of radiation. Please comment on the CPU board that was included in the course. I'm not saying that I can do any better but i would love to hear your commentary.
I have the example CPU board and in the picture below there is a small section of the area under the BGA. I have some issues with the length of the total path that the charge will need to travel. If you look at the picture attached, and please forgive my attempts to draw in "Paint", observe the green line. It starts at the H14 Pad and simulates where charge would be "likely" to go in a path from the voltage pad to the ground pad of the BGA. Starting at H14, charge (lets not quibble about positive charge vs negative charge) flows, at best, to the via then to the cap positive pad, then through the cap (not really, but lets go with it for the purposes of the argument) then to the GND pad of the cap, up through the GND via and finally ends at the GND pad of the BGA. That seems like a lot of path to travel. I have seen boards radiate at say 333 MHz where the radiation was stopped by tacking a 201 Cap in the right place.
Second, I am assuming that either layer L2 or L3 is GND (near as I can make out).Look at the yellow line starting from H14 again. That is in reality, an alternative path for charge. Ok, that might not be so bad because there is another cap, which shares the via. But, I question the connection of the Poly line that connects the vias. If there is a GND plane then this Poly line connection can be removed and a potentially large return path for charge can be avoided. I have blocked out this section of the Poly with green lines. Again, if there is a GND plane, I think that this connection should be removed.
I really hope to learn from your comments. My question is strictly on the basis of learning and as i have mentioned, i have seen just about every radiation problem that there is to see and I hope to avoid them in the future.
Please seen the attached picture.
Best Regards
Tom
I have the example CPU board and in the picture below there is a small section of the area under the BGA. I have some issues with the length of the total path that the charge will need to travel. If you look at the picture attached, and please forgive my attempts to draw in "Paint", observe the green line. It starts at the H14 Pad and simulates where charge would be "likely" to go in a path from the voltage pad to the ground pad of the BGA. Starting at H14, charge (lets not quibble about positive charge vs negative charge) flows, at best, to the via then to the cap positive pad, then through the cap (not really, but lets go with it for the purposes of the argument) then to the GND pad of the cap, up through the GND via and finally ends at the GND pad of the BGA. That seems like a lot of path to travel. I have seen boards radiate at say 333 MHz where the radiation was stopped by tacking a 201 Cap in the right place.
Second, I am assuming that either layer L2 or L3 is GND (near as I can make out).Look at the yellow line starting from H14 again. That is in reality, an alternative path for charge. Ok, that might not be so bad because there is another cap, which shares the via. But, I question the connection of the Poly line that connects the vias. If there is a GND plane then this Poly line connection can be removed and a potentially large return path for charge can be avoided. I have blocked out this section of the Poly with green lines. Again, if there is a GND plane, I think that this connection should be removed.
I really hope to learn from your comments. My question is strictly on the basis of learning and as i have mentioned, i have seen just about every radiation problem that there is to see and I hope to avoid them in the future.
Please seen the attached picture.
Best Regards
Tom
robertferanec , 12-17-2018, 09:21 AM
Hi Tom. You can find polygons connecting multiple power pins on the layer directly under BGA in many reference designs. When I was starting with HW design, I was not doing it. But when I saw it on many boards, I just use it - we have never had any problems with EMC due this. You can have a look at this server design which I was reviewing (have a look at the PCH chip): https://www.youtube.com/playlist?lis...3yeEbwVsNGU4jY
Paul van Avesaath , 12-19-2018, 02:45 AM
it used to be more of a problem (many years back) but with the current IC's it is more and more common that you do not need that direct decoupling beneath BGA components.
due to the fact that manufacturers put "on die decoupling caps" so close to were it needs to be.. outside of the BGA is more of a Bulk capacity..
i used to put 1 cap per power pin in my old designs.. now a days I am baffled by the low amount of caps needed.. I recently did the XCVU13P which is a very large chip. 5x5 @ 2104 pins.. and I basically only had to place decoupling around the IC since the recommendation stated that it need large bulk caps instead of the small ones.. I was sceptical to say the least.. but it works at top spec with no issues at all...
due to the fact that manufacturers put "on die decoupling caps" so close to were it needs to be.. outside of the BGA is more of a Bulk capacity..
i used to put 1 cap per power pin in my old designs.. now a days I am baffled by the low amount of caps needed.. I recently did the XCVU13P which is a very large chip. 5x5 @ 2104 pins.. and I basically only had to place decoupling around the IC since the recommendation stated that it need large bulk caps instead of the small ones.. I was sceptical to say the least.. but it works at top spec with no issues at all...
miner_tom , 12-19-2018, 08:48 AM
Paul, that's pretty amazing! Evidently the message has gotten through to IC manufacturers that things needed to change. Thanks for the photos.
Tom
Tom
Paul van Avesaath , 12-19-2018, 08:57 AM
yes, but it also has to do a lot with the increase of technology in chip design.. I wish i had a Hotline to the IC designers because in some cases they still make it nearly impossible two do a layout.. and it could be so easely fixed by swapping to balls on an BGA... but they will probably have their reasons for it too!
anovickis , 03-04-2019, 10:44 AM
On many of the larger xilinx parts there are small caps for HF decoupling built into the package, so a small bonus for paying a large price for the part
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