vias placement (0.1mm) clearance between vias
prabhu , 07-17-2018, 04:00 AM
Hello Everyone
I have designed my pcb but i would like to know some general sugesstions about the vias placement please see the attached picture below
two vias are place adjacent to each other with clearance of 0.1mm (no errors in DRC)
whether these kind of via placement are allowable or it will create any possibilities for short circuit after fabrications?
can anyone please explain me what is the use of this option in altium 17
force complete tenting on top and bottom
any explanations or suggestions would be greatly helpful for me
Thank you
prabhu
I have designed my pcb but i would like to know some general sugesstions about the vias placement please see the attached picture below
two vias are place adjacent to each other with clearance of 0.1mm (no errors in DRC)
whether these kind of via placement are allowable or it will create any possibilities for short circuit after fabrications?
can anyone please explain me what is the use of this option in altium 17
force complete tenting on top and bottom
any explanations or suggestions would be greatly helpful for me
Thank you
prabhu
Paul van Avesaath , 07-17-2018, 06:26 AM
- Force complete tenting on bottom - The term tenting means to close off. If this option is enabled then the settings in the applicable solder mask expansion design rule will be overridden, resulting in no opening in the solder mask on the bottom solder mask layer for this via. When this option is enabled, the Expansion value from rules and the Specify expansion value options are ignored.
Paul van Avesaath , 07-17-2018, 06:27 AM
0.1mm should work.. double checked a ddr3 design.. and spacing between Via's was the same
robertferanec , 07-18-2018, 09:06 AM
Only what is important, you do not want to drill closer than 0.2mm. Otherwise you should be fine.
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