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Double DDR routing in Fly-By topology
antonio.faraldi , 05-13-2018, 10:15 AM
Dear forum,
I'm following Fedevel Academy Advanced PCB Layout online course but I have some problems at Lesson 6 (1:01:58 Same data signal shared by two memories). I really don't understand how it's possible. You suggest to share the same VIA between pad of DDR3 placed on the top and the same pad of DDR3 placed on the bottom. But they have different nets! For example, after pin swapping of a data bit in the same byte of the DDR3 placed on the top, since the two pads are electricaly shorted by the VIA, I have to change the net of the pad on the bottom. But because of this operation, the two pads share the same data bit from processor. I think this is wrong. Infact in the schematic I have 64 data bits from processor and 4 DDR3 with 16 data bits. And so, none of the memories shares the same data bit from processor. Please help me. Can you explain me how it's possible? Thank you
robertferanec , 05-13-2018, 10:22 AM
I really don't understand how it's possible. You suggest to share the same VIA between pad of DDR3 placed on the top and the same pad of DDR3 placed on the bottom
- This is for Dual rank memory connection. It means, you have TOP and BOTTOM memory chips connected to same DATA bits, however they use different CHIPSELECT (CS0 vs CS1), CKE0 vs CKE1, etc .... If you are using single rank memory connection and you need to place memories on top of each other, these will not be sharing same data signals and will need to use uVIAs.
antonio.faraldi , 05-13-2018, 12:45 PM
Oh Robert thank you so much. I was going crazy.
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