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Confusion about a hole in pad and a via

flyforward , 01-16-2018, 01:12 PM
Hi Everyone,

I am confused with a hole in pads and a bare via. The confusion comes from the layout of a SOC with thermal release pad, where vias should be placed according to the layout recommendation from the datasheet as seen in the attachment (The first figure).

What will be the differences between placing pads with " multiple layers" (the third figure) and connect to "GND" Net, and just Vias through the board and connect to "GND" Net (the second figure)?

Thank you very much,


robertferanec , 01-16-2018, 06:18 PM
Do you mean place the VIAs/PADs during layout or in footprint library?

During layout I simply use VIAs, that is just easy - they will be automatically connected to the GND net. If I place there PADs, that would probably cause DRC (pad over pad) and also you would need to manually connect them to GND (that connection and pads would not be in schematic and that may cause problems when you will synchronize PCB with Schematic)

If in in footprint library, I do not place these in library, because I would like to be free to move them in case I need to route under the chip. Some people do it in library, but I am not really sure what they use.
flyforward , 01-17-2018, 03:22 PM

Thank you very much for your reply.

I simply used "pad" in the library for making the layout since it is recommended in the datasheet.

I tried to "put pads on top of pads" for making a hole in the pad and did not get DRC (as shown in this figure). I thought they may achieve the same goal here but not sure.

Thank you again

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