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Back Drilling - exported data question

popest , 11-05-2017, 05:56 AM

Do someone have experiences with back drilled VIAs in Altium? I have defined it for high speed (12.5Gbps) lines. Everything looks good except one thing. When I was checking exported gerbers data I saw, that in layers where the VIA is back drilled, Altium added copper with the same diameter like is the back-drill diameter. Do someone know why?

Here is an example for some inner layer in which the VIA will be drilled. Maybe it is due to mechanical support during drilling? If not, does exist some option in Altium how to remove it?

Thank you for the answer.

robertferanec , 11-06-2017, 02:17 PM
I have not used backdrilling, but I believe most PCB manufacturers automatically removes (suppress) unconnected pads an VIAs - so this should not be a problem for PCB manufacturing. But just in case, try to double check with your PCB manufacturer.

PS: One reason may be, that Altium leaves the pads there intentionally (e.g. maybe recognize which holes are backdrilled?), other reason could be, that it is a bug (?), ... possibly there may be other reasons? I am only guessing ...
popest , 11-06-2017, 02:27 PM
Hello Robert,

Thank you for the answer.Yes, it seems to be a bug. I have found in Altium forum similar problem with VIA in Gerber file. I have downloaded the trial version of ViewMate Pro which can remove unused pads. I did it, and it looks that it works fine, but I have little wonder if it is a good idea to do it by myself. What do you think?
robertferanec , 11-06-2017, 02:41 PM
Try to ask your PCB manufacturer if they will remove it. I would not remove it by myself, but if I wanted to be sure if in the PCB house they remove the correct pads, I would make a screenshot with notes and marked what I want them to remove or asked them to send me the gerbers after their adjustments.

PS: Possibly, I would try to find a way why it doesn't work in Altium (maybe older / new version of Altium is corrected, possibly there may be a new option to suppress the backdrilled VIAs (?))
popest , 11-06-2017, 03:03 PM
I am using the latest version of Altium (17.1.6). Maybe in Altium 18 it will be corrected. We will see soon.
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