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High Speed DDR3 Design

kushalrudra , 05-03-2016, 09:30 AM
Hi Robert

I had a quick question. Do you think routing layout for DD3 interface can hugely affect performance? if yes, how do i know that it is due to the PCB Design that performance has dropped? what sort of diagnosis tools would you use?

mairomaster , 05-03-2016, 10:30 AM
That is a huge topic but I can mention a few points.

It is very difficult. Currently we have tons of problem because of none-ideal LPDDR3 layout. As many people advice, it is important to try to do the layout as good as possible. In order to do that you should have a good understanding of how different things affect the signal integrity.

Before sending the design for manufacturing it is good to do a signal integrity simulation first. If a good software is used and it is properly set up, that could provide you with an idea of the signal integrity quality you will have.

After you have the board manufactured and the performance doesn't seem quite alright you can try a couple of different things. Depending on what processor you are using, it might have some integrated test utilities which could give you an idea about the performance of the different DDR lanes, error rates, etc. Apart from that, if you have access to some of the signals and a high speed oscilloscope ( >2 GHz of bandwidth, preferably more) you can try probing them and observing the signal quality.

But yeah, better not risk it and do your best at the layout stage. It saves a lot of time later on...
robertferanec , 05-04-2016, 12:23 AM
Originally posted by kushalrudra
Do you think routing layout for DD3 interface can hugely affect performance? if yes, how do i know that it is due to the PCB Design that performance has dropped?
I am not sure what do you mean by "reducing performance". Do you mean losing data? Normally, if data are lost - that's it, data are lost. It's not affecting performance, it's affecting reliability. There are some techniques what can help to identify the "bad" cases and try to fix them (e.g. by using ECC memory), but that really is not the way how a board should work. In most systems there is no way to detect and correct data corruption - that's why memory interface is so important. If it's not working correctly, it will not affect performance, but it may cause board crashing, resetting, freezing, ....

In our company, we do not have equipment to measure memory interface. We do a lot of testing instead. From my experience, if you are stressing the boards enough, and if there is a problem, you will find it. Here are some examples what we did with iMX6 Rex:
- Memory Stress testing in an Environmental chamber
- Stress tests

I highly recommend to run memory tests in Environmental chamber. I have seen many boards running with no errors for weeks in laboratory/office and failing within 1 hour in environmental chamber.

If we have to break too many design rules, we also simulate the layout (some of our clients have Hyperlynx - that is the software which I prefer for DDR3 simulation because it's relatively simple to use), but I have seen boards failing even after all the simulations were passing ok. As @mairomaster mentioned, the simulation must be properly set.

If you already have a DDR3 board and it's failing, you may need to run DDR3 calibration and you may want to play with register settings (there are plenty options which if they are not set correctly, the memory will not work ok)

The problem doesn't have to be layout, it could be register setting, but if you can not find a way to make it work, you may need to redesign the board (re-do layout, decoupling capacitor placement, stackup changes, reference voltages, termination, ... many factors can affect memory reliability).
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