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About changing the impedance profile following a new stack up

mulfycrowh , 07-01-2023, 02:01 PM
Hi everyone,

I have a design.
I decided to change the stackup.
Is there an easy way to update the new differential pairs profiles?
If I select the whole differential pair and then Route > Retrace Selected, AD very often destroys the previous design. Then you have to redesign and tune the new differential pair.
It is very time consuming.
Thanks for ideas.
mulfycrowh , 07-01-2023, 02:19 PM
In my case, I only need to change the width that becomes bigger, the gap remains unchanged to 127um.
qdrives , 07-01-2023, 02:48 PM
Perhaps shelving the polygon pours prior to selecting retrace?
mulfycrowh , 07-01-2023, 03:10 PM
For example, how would you manage the redesign of these differential pairs according to the new stackup.
I kindly remind that the width only has to be changed. The gap is unchanged.
qdrives , 07-02-2023, 01:09 PM
In the Altium presentations it always seems to work. Retrace does not do what I expect.
mulfycrowh , 07-02-2023, 01:39 PM
Retrace doesn't work at all.
For example, if you have a differential tuning on the pair, AD very often deletes the tuning!
In fact, except for single tracks, there is no interest to use Retrace.
The best way is to:

- make a copy of the project, run it with a second AD session and use it as a model.
- delete all the differential pairs you have to update in the first session and draw them again from scratch.

I have only 200 differential pairs to fix .................................................. ....
robertferanec , 07-03-2023, 07:33 AM
unfortunately, this is often learned by the hard way. Several times I mentioned on this forum, when I am routing I always use wider tracks and only adjust the proper width (make the tracks narower) after everything is routed. It is the same for diff pairs.

I had to change PCB manufacturers multiple times so I learned, there always has to be enough space around tracks to be able to change the width if needed.

In your case, I would just manually reroute them. Not really many other options.
mulfycrowh , 07-03-2023, 08:39 AM
@robertferanecThanks for reply.
My design is a 12 layers design with through holes.
I find that there are issues:
1/ The layer including PCIe signals between MXM board and CPU is very dense. Probably too much.
2/ I put a lot of GND vias in the design and the power polygon pours are often "cut" by these vias.

What do you think about the idea to use a 16 layers design involving through vias and also introduce buried and blind vias?

I saw your very interesting video with Rick but you don't speak about 16 layers.
What is for you the best 16 layers stack up?

Thanks.
qdrives , 07-03-2023, 12:51 PM
1) Make an ideas or bugcrunch at Atlium. Hopefully they will fix this (including the spacing for differential pairs).

2) But a bit like @robertferanec says, if you could live with just changing the width, you do not need to re-route them. However, it may make the spacing a bit wider as the center of the traces stays in place.

3) How about HDI? https://www.youtube.com/results?sear...ppy+holden+hdi
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