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how to specify current carrying capacity parameter for net
usernamezzz , 02-24-2022, 04:55 PM
Is there a way to specify the current carrying capacity for a net so that the design rules test willl tell you if you need more vias between planes or wider tracks
qdrives , 02-25-2022, 04:07 PM
The simple answer is NO.
Current through a trace and via will cause a temperature increase. What is your limit on temperature increase? How much cooling do you add? Is there a plane below the trace? What is the copper thickness? (Some could be answered with the layer stack in Altium for sure).
From the schematic it is possible to drive the rule for the width, but I personally will never do that as it does not allow narrow traces to other sections (like a small resistor for voltage measurement).
PCB toolkit allows you to estimate the current limit for a temperature rise. For vias you could use a simple rule of thumb: 1A for through hole via and 0.5A for micro via. And a 0.25mm track can carry 1A @ 10C increase. Whenever you need more current, than it is up to you.
The whole field of current carrying capability is not with hard data.
Current through a trace and via will cause a temperature increase. What is your limit on temperature increase? How much cooling do you add? Is there a plane below the trace? What is the copper thickness? (Some could be answered with the layer stack in Altium for sure).
From the schematic it is possible to drive the rule for the width, but I personally will never do that as it does not allow narrow traces to other sections (like a small resistor for voltage measurement).
PCB toolkit allows you to estimate the current limit for a temperature rise. For vias you could use a simple rule of thumb: 1A for through hole via and 0.5A for micro via. And a 0.25mm track can carry 1A @ 10C increase. Whenever you need more current, than it is up to you.
The whole field of current carrying capability is not with hard data.
usernamezzz , 02-25-2022, 05:00 PM
Thanks qdrives, that looks like an excellent tool
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