via in pad and DRC issues
gommer , 05-01-2021, 04:47 AM
You could think about via in pad when doing low pitch BGA fan-out, but I'm talking about e.g. a mounting hole shown below: via in pad for low inductance coupling between top and bottom and also in order to provide mechanical strength. The via's are defined in the footprint.
The problems I experience are twofold: first of all, I need to set the via to pad clearance to 0 in order for this to pass when placed on a PCB. I don't want to do this but if I don't, this component causes DRC clearance errors.
The 2nd problem that I encounter are another DRC error: Net Antennae: Via (...) from Top Layer to Bottom Layer. I understand that this suggests top and bottom are not on the same net, but in fact they are, it's all ground. It's as if these via's are no correctly electrically coupled to the pad. In footprint definition, i could not find a way to specifie this either.
There must be a way to do this correctly, these kind of electrically connected mechanical pads are common practice IMHO.
Any suggestions welcomed.
WhoKnewKnows , 05-01-2021, 09:01 PM
For the first issue, in the design rules, you can use Altium query language to have the rule ignore too small clearances for certain objects in the design. Or, you can write an entirely different additional rule for these objects and set it's priority higher than the default rule.
I think the net antennae issue may come from Altium seeing objects that it thinks needs to be connected by tracks. I've had similar issue where a polygon pour connects a few different things and it pours over these things correctly, but Altium still claims they're not connected or they're net antennae until I route tracks between them. Then it's happy.
gommer , 05-02-2021, 05:24 AM
About the clearance rule, I really can't find a good criteria to activate a rule in this case. I'd like the rule to be triggered by the footprint or component, but nothing seems to work.
And indeed I could get rid of the net antennae after repouring polygons and removing thermal relieves, but I don't know what actually cleared it. Needs some more experimenting.
WhoKnewKnows , 05-02-2021, 07:46 PM
Perhaps go back to the footprint and replace the vias with small TH pads. In the clearance rule there's a setting to ignore pad clearance within a footprint.
There are a couple strategies for what you want to do with rules. You can set the default clearance rule to exclude the special objects, and set the default rule's priority highest. Then have a lower priority rule that's only applied to the special cases (effectively excluding everything else).
gommer , 05-03-2021, 01:34 AM
That was a great suggestion. By replacing the via's with pads and setting all pad designators to 1, there's no need anymore for additional rules. Everything passes as Altium knows everything is the same net now.
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