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Track clearance with flex region cutout in Altium Designer

giacobbe_85 , 05-24-2020, 04:31 AM
In Altium Designer, I created a simple rigid-flex board with the 4 layers in the rigid part (top, in1, in2, bottom) and 2 layers in the flexible part (in1, in2).

I set 5mm clearance on a top layer track by means of a simple rule. On the rigid board, the track doesn't have 5mm clearance with respect to the board outline (which is the correct behaviour), but it has 5mm clearance with respect to the split line that divides the rigid part from the flex part.

Said in other words: I can route the track up to the very board border, except when it is a rigid-flex border.

How do I remove the 5mm clearance with respect to the border between the rigid and the flex part?

The error I get is "Celarance contraint between track on TopLayer and PolyRegion on MultiLater":

The net with the problem has class1 class; I set a simple 5mm clearance rule on this class. All other rules are set to Altium defaults:

The only way I found to remove the clearance violation is to set the clearance matrix as in the picture below, but this is not accepable for a standard circuit:

beamray , 05-24-2020, 04:05 PM
Wrong rule.
Rules- manufacturing - board outline clearance
giacobbe_85 , 05-25-2020, 01:13 AM
Thanks for the idea. Already tried to set all Board Outline Clearance to 0, it doesn't work.
beamray , 05-25-2020, 01:24 AM
What poly region does rule refers to?
Look at Rules and violations panel.

BTW what is your stackup? most likly one have not flex layers on top.
robertferanec , 05-25-2020, 01:25 AM
Interesting. I have not had this problem. Maybe try to click on advanced and set region to 0 ... but I am not sure if that is the right way to do it.
giacobbe_85 , 05-26-2020, 12:43 AM
@beamray , No, I don't have the flex no the top. This is my layer stackup:

I haven't set up any poly-region rule. Just a simple 5mm clearance rule for the track on top layer. For some reason, Altium considers the border between RIGID and FLEX as a poly-region, and therefore applies the clearance rule.

You can find attached the example project.

@robertferanec the only way I can disable the error is shown in the rule-matrix I posted before (last image of my first post), but this is not accepable in a design.
robertferanec , 05-28-2020, 06:18 AM
@giacobbe_85, is this your real stackup? I am not sure if that can be manufactured ... did you consult this with your PCB manufacturer?
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