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ale210 , 10-27-2019, 01:29 PM

Hi, I'm distributing a singal clock by a clock buffer (LMK00105 into 3 ADCs) the outputs needs to be 50 ohm matched impedance. So, the impedance of the output it's 50 Ohm, and the ADC it has an 30k ohm input (and 3.5 pF), in other forum they answers me with a parallel 50 ohm resistor should be enought, but matching the capacitive impedance it's difficult. How I can resolve this?

LMK00105 it has 5 single-ended outputs, then i feed the ENC+ pins of 3 LTC-2170 (with ENC-, tied to GND).

REgards

robertferanec , 10-28-2019, 12:57 PM

You may be able to simulate it: http://www.ti.com/product/LMK00105/toolssoftware

Altium simulator has some options to try different terminations, but Altium's simulator is not very accurate (normally I do not use it, but for this it may work).

What I would do, I would provide footprints for series termination on the beginning of the signal (and used 22 OHM resistor) and I would provide unfitted empty footprints for possible parallel termination (if needed), but serial termination is usually ok - may depend also on frequency and length of the clock.

ale210 , 10-28-2019, 03:34 PM

Hi Robert, finally did you edited the sheet template? I'm the guy who answered you in your video.

Back to the subject, I'm using Altium SI for simulate it, but gives me a confusing results (at least for me), because the DS of LMK00105 says: Rs = Zo - Ro, but I'm confused because transmission line Zo = 50R and output impedance Ro=50R gives me 0R, however without termination the signal has huge overvoltage, and with series termination of 50R gives me "better result" see attached picture, but as you can see in the middle of the signal rises, a step occurs.

Digging in internet, this step it's normal with serial termination, also I can use a parallel rather than serial res, but the signal it's Vdd/2 (resistor divider serial 50 OHm of the output device and 50 Ohm parallel to GND).

Finally as I always do: series resistor about 33 Ohms, because it's not consider transmission line since clock it's about 13 MHz and the lenght of the track around 65 mm, and the 1/10 of the signal lenght it's about 130 mm.

Baby_1 , 11-01-2019, 11:22 AM

Hi,
Did you design a 50 ohm transmission line? at your frequency the input reactance is low(3.5pf) don't think of it.

Could you provide us a schematic of your mentioned circuit? because it is not clear enough to help you on this issue.

robertferanec , 11-04-2019, 08:21 AM

- do you mean the title block? I have not created templates, currently trying to figure out the best way to work with database library in Altium

I can't help much with Altium simulation, I do not use it. Usually I use Hyperlynx and there I usually just assign both models and run a pulse through it, Then if needed I play with different terminations.