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DDR3 termination with DSP.
atta , 07-25-2019, 04:04 PM
Hi ..
I am working with DSP with DDR3 SDRAM. Ti (texas instrument ) platform has two evaluation board of DSP .
I evaluate both evaluation board schematic and found a difference in DDR3 termination .
1-- In first schematic DDR3 SDRAM termination resistors with capacitor one end VTT , other end "DGND"
2-- In second schematic termination resistors with capacitor other end connected with "1.35V" net name (VDDS_DDR_K2G). instead of "DGND".
* What is the difference in both techniques , and which technique is better. scematic samples are shown below.
Thanks
I am working with DSP with DDR3 SDRAM. Ti (texas instrument ) platform has two evaluation board of DSP .
I evaluate both evaluation board schematic and found a difference in DDR3 termination .
1-- In first schematic DDR3 SDRAM termination resistors with capacitor one end VTT , other end "DGND"
2-- In second schematic termination resistors with capacitor other end connected with "1.35V" net name (VDDS_DDR_K2G). instead of "DGND".
* What is the difference in both techniques , and which technique is better. scematic samples are shown below.
Thanks
robertferanec , 07-30-2019, 02:03 AM
I believe, this depends on layout and which of these is used as the reference plane for the ADDR/CMD/CTL signals. Have a look at layout of those boards and please let me know.
PS: In many schematics I use both - GND and also VTT as I have VTT reference plane on one side and GND on the other side.
PS: In many schematics I use both - GND and also VTT as I have VTT reference plane on one side and GND on the other side.
atta , 10-13-2019, 03:28 PM
Hi
Robert i searched from different papers and processor manufacturers (TI). they recommended capacitor should decoupled with DDR (1.35~1.5V) voltage instead of GND.
Robert i searched from different papers and processor manufacturers (TI). they recommended capacitor should decoupled with DDR (1.35~1.5V) voltage instead of GND.
atta , 10-13-2019, 04:19 PM
Hai
Sir ! i want to create new post but new post button is not show to me.
> 32 bit Processor's DDR3 module interface is connected with FPGA and RAM as per attached picture.
> As per recommendation I routed address +cntrl +clk signals as FLY -By topolgy.
>Now in my case 32 bit data bus is shared between FPGA and 16bit RAM as shown in attached picture.
please recommend which topology should i follow for data bus . (is T_branched point to point topology worked for me ?)
thanks
Sir ! i want to create new post but new post button is not show to me.
> 32 bit Processor's DDR3 module interface is connected with FPGA and RAM as per attached picture.
> As per recommendation I routed address +cntrl +clk signals as FLY -By topolgy.
>Now in my case 32 bit data bus is shared between FPGA and 16bit RAM as shown in attached picture.
please recommend which topology should i follow for data bus . (is T_branched point to point topology worked for me ?)
thanks
Paul van Avesaath , 10-15-2019, 02:14 AM
just curious how you think this should work.. a shared databus is something i have never seen on a DDR controller.. either the DSP is the host controller or the FPGA not a combination of both...
Comments:
atta, 10-22-2019, 11:44 AM
> DSP will be HOST controller . > FPGA will be taking data from different sensors . after aligning and synchronizing data will be sent to DSP for processing. > Optionally! If code (algorithm) will large enough , so that it will not be accommodate in DSP's internal RAM. than external 16 bit ram will be used as shown in above attached picture.regards atta
robertferanec , 10-16-2019, 04:40 AM
@atta what are you trying to do? How it should work?
atta , 10-22-2019, 11:45 AM
> DSP will be HOST controller .
> FPGA will be taking data from different sensors . after aligning and synchronizing data will be sent to DSP for processing.
> Optionally! If code (algorithm) will large enough , so that it will not be accommodate in DSP's internal RAM. than external 16 bit ram will be used as shown in above attached picture.
regards
atta
> FPGA will be taking data from different sensors . after aligning and synchronizing data will be sent to DSP for processing.
> Optionally! If code (algorithm) will large enough , so that it will not be accommodate in DSP's internal RAM. than external 16 bit ram will be used as shown in above attached picture.
regards
atta
robertferanec , 10-23-2019, 01:19 AM
If I understand right, it looks to me like you are trying to use DDR3 bus as a peripheral bus. DDR3 is using special communication protocol - it is not working the same way as a standard bus. So for communication between DSP <-> FPGA you may want to use something else and not DDR3 interface. If your FPGA needs additional RAM, you may want to use a separate DRAM chip for this and conenct it to FPGA only.
DDR3 <-> DSP <-> FPGA <-> RAM
DDR3 <-> DSP <-> FPGA <-> RAM
atta , 11-02-2019, 11:17 AM
Thanks for answer. It seems logical . You understand right.
please let me clear . If RAM is required for DSP and FPGA as well . Separate RAMs will be connected for each.
> One RAM with DSP . which is controller by DSP DDR3 controller module.
> 2nd RAM with FPGA , which is controlled by FPGA DDR3 controller module.
please let me clear . If RAM is required for DSP and FPGA as well . Separate RAMs will be connected for each.
> One RAM with DSP . which is controller by DSP DDR3 controller module.
> 2nd RAM with FPGA , which is controlled by FPGA DDR3 controller module.
Paul van Avesaath , 11-02-2019, 01:09 PM
You are correct! 
robertferanec , 11-03-2019, 11:47 AM
Separate RAMs will be connected for each.
atta , 11-04-2019, 12:46 PM
There is another option available, if I use One DRAM.
>First step > FPGA Write data from to DRAM through DDR interface. (16 bit).
> 2nd step > DSP read data from same DRAM through DDR interface. (16 bit).
Is it feasibility exist ?
>First step > FPGA Write data from to DRAM through DDR interface. (16 bit).
> 2nd step > DSP read data from same DRAM through DDR interface. (16 bit).
Is it feasibility exist ?
Paul van Avesaath , 11-04-2019, 01:08 PM
This is just not how this works.. You could only do this if you could tristate all io of the dsp and fpga.. And routing would be a disaster.. (there would be massive stubbs) very slow speed and I actually don't think you could get this to work...
A better way would be to make the fpga The host to the ddr3.. And add another interface between the fpga and the dsp so dsp can access the ddr3 through the fpga.. Like Robert mentioned like before..
A better way would be to make the fpga The host to the ddr3.. And add another interface between the fpga and the dsp so dsp can access the ddr3 through the fpga.. Like Robert mentioned like before..
robertferanec , 11-06-2019, 03:02 AM
@atta ddr3 bus is not a peripheral bus. It is a bus designed to work between CPU/FPGA (memory controller) and memory chips. DDR3 is not designed for sharing the bus.
Paul van Avesaath , 11-06-2019, 03:05 AM
You could have a look at the hybrid memory cube.. That allows multiple hosts.. But it's very expensive, not big.. But very fast
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