VIAs under THERMAL PAD DRC
Naveen-Krishnan , 04-08-2019, 03:57 AM
The PCB fabrication plant, wants me to maintain 0.2mm clearance between VIAS and PADS of same net and any net. Hence I created rules like in the following picture :
The problem what I am facing is, Altium throws error for the VIAS under the thermad pad of QFN. I couldn't find out how to solve this problem, could anyone help me out please !
Thanks in advance.
mairomaster , 04-09-2019, 03:16 AM
If you scroll down, in one of the other categories you have a special Via Under SMD rule.
Naveen-Krishnan , 04-09-2019, 03:30 AM
I tried enabling VIAS under SMD PAD, but still the Altium shows DRC error : Clearance contraint.
mairomaster , 04-09-2019, 04:51 AM
Add an exception for the particular footprint.
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