Originally posted by robertferanec
Thank you for your reply.
I know that T-branch could be not the right topology, but the board i'm trying to design it's a demo board where i should mount another board on the bus interface.
I'm using this board to practice with High Speed design and i wanna follow all possible rules to design it properly.
I'm using a STM32F7 uC with a 32bit bus to connect a Sdram, a Nand Flash and a transceiver chip.
In this first stage, the transceiver chip will be connected through its demo board (attached picture, AXM88180-EVB-RTL8211E-1 SMDK2440 , from Asix), but in the final design it will be placed directly on the my PCB, my company has the End User Agreement to use it.
I'm little confused about the topology i should use.
I have a demo board of the STM32F7 (attached picture, cadence pcb) , where the bus is connected in a similar way, first with two connectors and then to memory chips (nand and sdram).
is it better to use a fly-by topology i suppose in order to avoid reflections ?
Maybe i can route hte bus in some way first to the connectors i have to use for the demo board plug, and then to the memory chips trying to tune them (fly-by) ?? ...
I just wanna solve this before proceed with consideration about timings. Some people in other forums told me that probably some reflections will occours, but even without using High Speed Design rules it should work.. I'm not shure about this, anymay i have to practice with High Speed Design and i want to to things in the right way.. at least i want to try...