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Calculating Correct Length for mDDR Clock Signals

mohammadniaraki , 11-06-2015, 11:49 PM
Dear Robert,
I’m Designing a Core Board For Samsung S3C6410. I has been used two K4X1G163PE-FGC6 for External DRAM(s) (@133mhz).
I’ve attached my PCB Stack up.

I have to route Dram Clocks with 100ohms Diff. Pair Impedance. So according to my stack up I should route them in top layer or in bottom layer but I’m worry about EMI test. I can route them in inner layers with approximately 90ohms but reflection issue can occurred.
What do you think? Which one is suitable for me?
I’ve Another questions.
I think the length of DDR clocks should be 2 times of maximum length of the longest signal in data groups. Does it correct? Is there any method for calculating the correct length of DDR clocks?
Is Length matching critical for crystal traces? Where is the suitable places for load capacitors ? what is the best method for routing crystal signals?
I routed 25Mhz crystal of DM9000AEP (LAN Phy.) Like Below image.

is it a Correct Layout for that?
Any helpful recommendation is important for me.

Thank you very much indeed for your help.

Best regards
robertferanec , 11-09-2015, 01:44 AM
1) We do route clocks on top/bottom very often. If these differential pair signals are routed properly and you keep the required impedance, you should be fine. We never had EMI problems with it.

2) Clock length: I am not sure what your design guide says, but I don't think I have seen requirement like that ( "clocks should be 2 times of maximum length of the longest signal in data groups"). In most boards which I have routed, the clock was just the longest signal, but it didn't have to be as long as twice of longest data signal.

3) We do not do "waves" on crystal signals. I normally place load capacitors on the tracks on the way to the crystal. Here is an example how we normally route crystals:

mohammadniaraki , 11-09-2015, 04:20 AM
thanks a lot.
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